R
Spartan-IIE FPGA Family: Functional Description
If CCLK is slower than FCCNH, the FPGA will never assert
BUSY. In this case, the above handshake is unnecessary,
and data can simply be entered into the FPGA every CCLK
cycle.
tions. However, to avoid aborting configuration, WRITE
must continue to be asserted while CS is asserted during
CCLK transitions.
Abort
To abort configuration during a write sequence, deassert
WRITE while holding CS Low. The abort operation is initi-
ated at the rising edge of CCLK. The device will remain
BUSY until the aborted operation is complete. After aborting
configuration, data is assumed to be unaligned to word
boundaries and the FPGA requires a new synchronization
word prior to accepting any new packets.
After INIT
Goes High
User Drives
WRITE and CS
Low
Boundary-Scan Configuration Mode
In the boundary-scan mode, no nondedicated pins are
required, configuration being done entirely through the
IEEE 1149.1 Test Access Port (TAP).
Load One
Configuration
Byte on Next
CCLK Rising Edge
Configuration through the TAP uses the special CFG_IN
instruction. This instruction allows data input on TDI to be
converted into data packets for the internal configuration
bus.
The following steps are required to configure the FPGA
through the boundary-scan port.
FPGA
Yes
Driving BUSY
High?
1. Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
No
2. Enter the Shift-DR (SDR) state
3. Shift a standard configuration bitstream into TDI
4. Return to Run-Test-Idle (RTI)
End of
Configuration
Data File?
No
5. Load the JSTART instruction into IR
6. Enter the SDR state
Yes
7. Clock TCK (if selected) through the startup sequence
(the length is programmable)
User Drives
WRITE and CS
High
8. Return to RTI
Configuration and readback via the TAP is always available.
The boundary-scan mode simply locks out the other modes.
The boundary-scan mode is selected by a <10x> on the
mode pins (M0, M1, M2). Note that the PROGRAM pin must
be pulled High prior to reconfiguration. A Low on the PRO-
GRAM pin resets the TAP controller and no boundary scan
operations can be performed. See Xilinx Application Note
XAPP188 for more information on boundary-scan configu-
ration.
To CRC Check
DS001_19_032300
Figure 21: Loading Configuration Data for the Slave
Parallel Mode
Readback
A configuration packet does not have to be written in one
continuous stretch, rather it can be split into many write
sequences. Each sequence would involve assertion of CS.
The configuration data stored in the Spartan-IIE FPGA con-
figuration memory can be read back for verification. Along
with the configuration data it is possible to read back the
contents of all flip-flops/latches, LUT RAMs, and block
RAMs. This capability is used for real-time debugging.
In applications where multiple clock cycles may be required
to access the configuration data before each byte can be
loaded into the Slave Parallel interface, a new byte of data
may not be ready for each consecutive CCLK edge. In such
a case the CS signal may be deasserted until the next byte
is valid on D0-D7. While CS is High, the Slave Parallel inter-
face does not expect any data and ignores all CCLK transi-
For more detailed information see Xilinx Application Note
XAPP176, Configuration and Readback of the Spartan-II
and Spartan-IIE FPGA Families.
28
www.xilinx.com
DS077-2 (v2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
