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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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Spartan-IIE FPGA Family: Functional Description  
The Spartan-IIE FPGA LUT can also provide a 16-bit shift  
register that is ideal for capturing high-speed or burst-mode  
data. This mode can also be used to store data in applica-  
tions such as Digital Signal Processing.  
Configurable Logic Block  
The basic building block of the Spartan-IIE FPGA CLB is the  
logic cell (LC). An LC includes a 4-input function generator,  
carry logic, and storage element. The output from the func-  
tion generator in each LC drives the CLB output or the  
D input of the flip-flop. Each Spartan-IIE FPGA CLB con-  
tains four LCs, organized in two similar slices; a single slice  
is shown in Figure 6.  
Storage Elements  
Storage elements in the Spartan-IIE FPGA slice can be  
configured either as edge-triggered D-type flip-flops or as  
level-sensitive latches. The D inputs can be driven either by  
function generators within the slice or directly from slice  
inputs, bypassing the function generators.  
In addition to the four basic LCs, the Spartan-IIE FPGA CLB  
contains logic that combines function generators to provide  
functions of five or six inputs.  
In addition to Clock and Clock Enable signals, each slice  
has synchronous set and reset signals (SR and BY). SR  
forces a storage element into the initialization state speci-  
fied for it in the configuration. BY forces it into the opposite  
state. Alternatively, these signals may be configured to  
operate asynchronously.  
Look-Up Tables  
Spartan-IIE FPGA function generators are implemented as  
4-input look-up tables (LUTs). In addition to operating as a  
function generator, each LUT can provide a 16 x 1-bit syn-  
chronous RAM. Furthermore, the two LUTs within a slice  
can be combined to create a 16 x 2-bit or 32 x 1-bit syn-  
chronous RAM, or a 16 x 1-bit dual-port synchronous RAM.  
All control signals are independently invertible, and are  
shared by the two flip-flops within the slice.  
DS077-2 (v2.3) June 18, 2008  
www.xilinx.com  
13  
Product Specification  
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