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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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Spartan-IIE FPGA Family: Functional Description  
is required for most output standards and for LVTTL,  
LVCMOS, and PCI inputs.  
Hot Swap, Hot Insertion, Hot Socketing Support  
The I/O pins support hot swap — also called hot insertion  
and hot socketing — and are considered CompactPCI  
Friendly according to the PCI Bus v2.2 Specification. Con-  
sequently, an unpowered Spartan-IIE FPGA can be  
plugged directly into a powered system or backplane with-  
out affecting or damaging the system or the FPGA. The hot  
swap functionality is built into every XC2S150E,  
XC2S400E, and XC2S600E device. All other Spartan-IIE  
devices built after Product Change Notice PCN2002-05 also  
include hot swap functionality.  
Table 4: Compatible Standards  
VCCO  
Compatible Standards  
3.3V  
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP,  
LVPECL, GTL, GTL+  
2.5V  
SSTL2 I, SSTL2 II, LVCMOS2, LVDS, Bus  
LVDS, GTL, GTL+  
1.8V  
1.5V  
LVCMOS18, GTL, GTL+  
To support hot swap, Spartan-IIE devices include the follow-  
ing I/O features.  
HSTL I, HSTL III, HSTL IV, GTL, GTL+  
Signals can be applied to Spartan-IIE FPGA I/O pins  
before powering the FPGA’s VCCINT or VCCO supply  
inputs.  
Spartan-IIE FPGA I/O pins are high-impedance (i.e.,  
three-stated) before and throughout the power-up and  
configuration processes when employing a  
configuration mode that does not enable the  
preconfiguration weak pull-up resistors (see Table 11,  
page 22).  
Some input standards require a user-supplied threshold  
voltage, VREF. In this case, certain user-I/O pins are auto-  
matically configured as inputs for the VREF voltage. About  
one in six of the I/O pins in the bank assume this role.  
VREF pins within a bank are interconnected internally and  
consequently only one VREF voltage can be used within  
each bank. All VREF pins in the bank, however, must be con-  
nected to the external voltage source for correct operation.  
In a bank, inputs requiring VREF can be mixed with those  
that do not but only one VREF voltage may be used within a  
bank. The VCCO and VREF pins for each bank appear in the  
device pinout tables.  
There is no current path from the I/O pin back to the  
V
CCINT or VCCO voltage supplies.  
Spartan-IIE FPGAs are immune to latch-up during hot  
swap.  
Within a given package, the number of VREF and VCCO pins  
can vary depending on the size of device. In larger devices,  
more I/O pins convert to VREF pins. Since these are always  
a superset of the VREF pins used for smaller devices, it is  
possible to design a PCB that permits migration to a larger  
device. All VREF pins for the largest device anticipated must  
be connected to the VREF voltage, and not used for I/O.  
Once connected to the system, each pin adds a small  
amount of capacitance (CIN). Likewise, each I/O consumes  
a small amount of DC current, equivalent to the input leak-  
age specification (IL). There also may be a small amount of  
temporary AC current (IHSPO) when the pin input voltage  
exceeds VCCO plus 0.4V, which lasts less than 10 ns.  
A weak-keeper circuit within each user-I/O pin is enabled  
during the last frame of configuration data and has no  
noticeable effect on robust system signals driven by an  
active driver or a strong pull-up or pull-down resistor.  
Undriven or floating system signals may be affected. The  
specific effect depends on how the I/O pin is configured.  
User-I/O pins configured as outputs or enabled outputs  
have a weak pull-up resistor to VCCO during the last config-  
uration frame. User-I/O pins configured as inputs or bidirec-  
tional I/Os have weak pull-down resistors. The weak-keeper  
circuit turns off when the DONE pin goes High, provided  
that it is not used in the configured application.  
Table 5: I/O Banking  
FT256, FG456,  
Package  
VCCO Banks  
VREF Banks  
TQ144, PQ208  
Interconnected as 1  
8 independent  
FG676  
8 independent  
8 independent  
See Xilinx® Application Note XAPP179 for more information  
on I/O resources.  
12  
www.xilinx.com  
DS077-2 (v2.3) June 18, 2008  
Product Specification  
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