R
Spartan-IIE FPGA Family: Functional Description
•
•
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in Figure 10.
Dedicated Routing
Some classes of signal require dedicated routing resources
to maximize performance. In the Spartan-IIE FPGA archi-
tecture, dedicated routing resources are provided for two
classes of signal.
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.
3-State
Lines
CLB
CLB
CLB
CLB
DS001_07_090600
Figure 10: BUFT Connections to Dedicated Horizontal Bus Lines
selected either from these pads or from signals in the gen-
eral purpose routing.
Global Routing
Global Routing resources distribute clocks and other sig-
nals with very high fanout throughout the device. Spar-
tan-IIE devices include two tiers of global routing resources
referred to as primary and secondary global routing
resources.
GCLKPAD2
GCLKBUF2
GCLKPAD3
GCLKBUF3
Global
Clock Rows
Global Clock
Column
•
The primary global routing resources are four
dedicated global nets with dedicated input pins that are
designed to distribute high-fanout clock signals with
minimal skew. Each global clock net can drive all CLB,
IOB, and block RAM clock pins. The primary global
nets may only be driven by global buffers. There are
four global buffers, one for each global net.
Global Clock
Spine
•
The secondary global routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across the bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These secondary resources
are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
DS001_08_060100
Figure 11: Global Clock Distribution Network
Clock Distribution
Delay-Locked Loop (DLL)
The Spartan-IIE family provides high-speed, low-skew clock
distribution through the primary global routing resources
described above. A typical clock distribution net is shown in
Figure 11.
Associated with each global clock input buffer is a fully digi-
tal Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
networks. The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element
(Figure 12). Additional delay is introduced such that clock
edges reach internal flip-flops exactly one clock period after
they arrive at the input. This closed-loop system effectively
eliminates clock-distribution delay by ensuring that clock
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
DS077-2 (v2.3) June 18, 2008
www.xilinx.com
17
Product Specification
XILINX [ XILINX, INC ]
