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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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Spartan-IIE FPGA Family:  
Functional Description  
DS077-2 (v2.3) June 18, 2008  
0
Product Specification  
As can be seen in Figure 3, the CLBs form the central logic  
structure with easy access to all support and routing struc-  
tures. The IOBs are located around all the logic and mem-  
ory elements for easy and quick routing of signals on and off  
the chip.  
Architectural Description  
Spartan-IIE FPGA Array  
The Spartan®-IIE user-programmable gate array, shown in  
Figure 3, is composed of five major configurable elements:  
Values stored in static memory cells control all the config-  
urable logic elements and interconnect resources. These  
values load into the memory cells on power-up, and can  
reload if necessary to change the function of the device.  
IOBs provide the interface between the package pins  
and the internal logic  
CLBs provide the functional elements for constructing  
most logic  
Each of these elements will be discussed in detail in the fol-  
lowing sections.  
Dedicated block RAM memories of 4096 bits each  
Clock DLLs for clock-distribution delay compensation  
and clock domain control  
Versatile multi-level interconnect structure  
DLL  
DLL  
CLBs  
CLBs  
CLBs  
CLBs  
DLL  
DLL  
I/O LOGIC  
DS077_01_052102  
Figure 3: Basic Spartan-IIE Family FPGA Block Diagram  
© 2003-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other  
trademarks are the property of their respective owners.  
DS077-2 (v2.3) June 18, 2008  
www.xilinx.com  
9
Product Specification  
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