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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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Spartan-IIE FPGA Family: Functional Description  
Optional pull-up and pull-down resistors and an optional  
weak-keeper circuit are attached to each user I/O pad. Prior  
to configuration all outputs not involved in configuration are  
forced into their high-impedance state. The pull-down resis-  
tors and the weak-keeper circuits are inactive, but inputs  
may optionally be pulled up. The activation of pull-up resis-  
tors prior to configuration is controlled on a global basis by  
the configuration mode pins. If the pull-up resistors are not  
activated, all the pins will float. Consequently, external  
pull-up or pull-down resistors must be provided on pins  
required to be at a well-defined logic level prior to configura-  
tion.  
can be used in close proximity to each other. See I/O Bank-  
ing.  
An optional weak-keeper circuit is connected to each out-  
put. When selected, the circuit monitors the voltage on the  
pad and weakly drives the pin High or Low to match the  
input signal. If the pin is connected to a multiple-source sig-  
nal, the weak keeper holds the signal in its last state if all  
drivers are disabled. Maintaining a valid logic level in this  
way helps eliminate bus chatter.  
Because the weak-keeper circuit uses the IOB input buffer  
to monitor the input level, an appropriate VREF voltage must  
be provided if the signaling standard requires one. The pro-  
vision of this voltage must comply with the I/O banking  
rules.  
All pads are protected against damage from electrostatic  
discharge (ESD) and from over-voltage transients. After  
configuration, clamping diodes are connected to VCCO for  
LVTTL, PCI, HSTL, SSTL, CTT, and AGP standards.  
I/O Banking  
Some of the I/O standards described above require VCCO  
and/or VREF voltages. These voltages are externally sup-  
plied and connected to device pins that serve groups of  
IOBs, called banks. Consequently, restrictions exist about  
which I/O standards can be combined within a given bank.  
All Spartan-IIE FPGA IOBs support IEEE 1149.1-compati-  
ble boundary scan testing.  
Input Path  
A buffer in the IOB input path routes the input signal directly  
to internal logic and through an optional input flip-flop.  
Eight I/O banks result from separating each edge of the  
FPGA into two banks (see Figure 5). The pinout tables  
show the bank affiliation of each I/O (see Pinout Tables,  
page 53). Each bank has multiple VCCO pins which must be  
connected to the same voltage. Voltage requirements are  
determined by the output standards in use.  
An optional delay element at the D-input of this flip-flop elim-  
inates pad-to-pad hold time. The delay is matched to the  
internal clock-distribution delay of the FPGA, and when  
used, assures that the pad-to-pad hold time is zero.  
Each input buffer can be configured to conform to any of the  
low-voltage signaling standards supported. In some of  
these standards the input buffer utilizes a user-supplied  
threshold voltage, VREF. The need to supply VREF imposes  
constraints on which standards can used in close proximity  
to each other. See I/O Banking.  
Bank 0  
Bank 1  
GCLK3 GCLK2  
There are optional pull-up and pull-down resistors at each  
input for use after configuration.  
Spartan-IIE  
Device  
Output Path  
The output path includes a 3-state output buffer that drives  
the output signal onto the pad. The output signal can be  
routed to the buffer directly from the internal logic or through  
an optional IOB output flip-flop.  
GCLK1 GCLK0  
The 3-state control of the output can also be routed directly  
from the internal logic or through a flip-flip that provides syn-  
chronous enable and disable.  
Bank 5  
Bank 4  
DS077-2_02_051501  
Each output driver can be individually programmed for a  
wide range of low-voltage signaling standards. Each output  
buffer can source up to 24 mA and sink up to 48 mA. Drive  
strength and slew rate controls minimize bus transients. The  
default output driver is LVTTL with 12 mA drive strength and  
slow slew rate.  
Figure 5: Spartan-IIE I/O Banks  
In the TQ144 and PQ208 packages, the eight banks have  
VCCO connected together. Thus, only one VCCO level is  
allowed in these packages, although different VREF values  
are allowed in each of the eight banks.  
In most signaling standards, the output high voltage  
depends on an externally supplied VCCO voltage. The need  
to supply VCCO imposes constraints on which standards  
Within a bank, standards may be mixed only if they use the  
same VCCO. Compatible standards are shown in Table 4.  
GTL and GTL+ appear under all voltages because their  
open-drain outputs do not depend on VCCO. Note that VCCO  
DS077-2 (v2.3) June 18, 2008  
www.xilinx.com  
11  
Product Specification  
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