R
Spartan-IIE FPGA Family: Functional Description
COUT
YB
Y
I4
I3
I2
I1
G4
G3
G2
G1
S
R
Look-Up
Table
YQ
D
Q
Carry
and
Control
Logic
O
CK
EC
F5IN
BY
SR
XB
X
F4
F3
F2
F1
I4
I3
I2
I1
S
R
Look-Up
Table
XQ
D
Q
Carry
and
Control
Logic
O
CK
EC
BX
CIN
CLK
CE
DS001_04_091400
Figure 6: Spartan-IIE CLB Slice (two identical slices in each CLB)
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the two
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.
Additional Logic
The F5 multiplexer in each slice combines the function gen-
erator outputs (Figure 7). This combination provides either
a function generator that can implement any 5-input func-
tion, a 4:1 multiplexer, or selected functions of up to nine
inputs.
14
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DS077-2 (v2.3) June 18, 2008
Product Specification
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