R
XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 3
IEEE 1149.1 Boundary-Scan (JTAG)
The XC18V00 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required Boundary-Scan instructions, as well as many of
the optional instructions specified by IEEE Std. 1149.1. In
addition, the JTAG interface is used to implement in-system
programming (ISP) to facilitate configuration, erasure, and
verification operations on the XC18V00 device.
lists the required and optional Boundary-Scan
instructions supported in the XC18V00. Refer to the IEEE Std.
1149.1 specification for a complete description of Boundary-
Scan architecture and the required and optional instructions.
Table 4:
Boundary-Scan Instructions
Boundary-Scan
Command
BYPASS
SAMPLE/
PRELOAD
EXTEST
IR[7:5]
TDI
→
Notes:
1.
IR[4]
ISP
Status
IR[3]
Security
IR[2]
0
IR[1:0]
01
(1)
→
TDO
000
IR[1:0] =
01
is specified by IEEE Std. 1149.1
Figure 3:
Instruction Register Values Loaded into IR as
Part of an Instruction Scan Sequence
Boundary-Scan Register
The Boundary-Scan register is used to control and observe
the state of the device pins during the EXTEST,
SAMPLE/PRELOAD, and CLAMP instructions. Each output
pin on the XC18V00 has two register stages that contribute
to the Boundary-Scan register, while each input pin only has
one register stage.
For each output pin, the register stage nearest to TDI controls
and observes the output state, and the second stage closest to
TDO controls and observes the high-Z enable state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
Binary
Code [7:0]
Description
Required Instructions:
11111111
Enables BYPASS
00000001
Enables Boundary-Scan
SAMPLE/PRELOAD
operation
00000000
Enables Boundary-Scan
EXTEST operation
11111010
Enables Boundary-Scan
CLAMP operation
11111100
All outputs in high-Z state
simultaneously
11111110
Enables shifting out
32-bit IDCODE
11111101
Enables shifting out
32-bit USERCODE
11101110
Initiates FPGA configuration
by pulsing CF pin Low once
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for
examination by using the IDCODE instruction. The IDCODE
is available to any other system component via JTAG.
See
for the XC18V00 IDCODE values.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
Optional Instructions:
CLAMP
HIGHZ
IDCODE
USERCODE
XC18V00 Specific Instructions:
CONFIG
where
v
=
the die version number
f
=
the family code (50h for XC18V00 family)
a
=
the ISP PROM product ID (26h or 36h for the XC18V04)
c
=
the company code (49h for Xilinx)
Note:
The LSB of the IDCODE register is always read as logic “1”
as defined by IEEE Std. 1149.1.
Instruction Register
The Instruction Register (IR) for the XC18V00 is eight bits
wide and is connected between TDI and TDO during an
instruction scan sequence. In preparation for an instruction
scan sequence, the instruction register is parallel loaded with
a fixed instruction capture pattern. This pattern is shifted out
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI. The detailed composition of the
instruction capture pattern is illustrated in
The ISP Status field, IR(4), contains logic “1” if the device is
currently in ISP mode; otherwise, it contains logic “0”. The
Security field, IR(3), contains logic “1” if the device has been
programmed with the security option turned on; otherwise, it
contains logic “0”.
lists the IDCODE register values for XC18V00 devices.
Table 5:
IDCODES Assigned to XC18V00 Devices
ISP-PROM
XC18V01
XC18V02
XC18V04
XC18V512
Notes:
1.
The
<v>
in the IDCODE field represents the device’s revision
code (in hex), and may vary.
IDCODE
05024093h
05025093h
05026093h
05023093h
or
or
or
or
<v>5034093h
<v>5035093h
<v>5036093h
<v>5033093h
DS026 (v5.2) January 11, 2008
Product Specification
7
XILINX [ XILINX, INC ]
