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XC18V01VQ44C0936 参数 Datasheet PDF下载

XC18V01VQ44C0936图片预览
型号: XC18V01VQ44C0936
PDF下载: 下载PDF文件 查看货源
内容描述: [Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44]
分类和应用: 内存集成电路
文件页数/大小: 24 页 / 316 K
品牌: XILINX [ XILINX, INC ]
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R
XC18V00 Series In-System-Programmable Configuration PROMs
The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information
about the device’s programmed contents. By using the USERCODE instruction, a user-programmable identification code
can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XC18V00
device. If the device is blank or was not loaded during programming, the USERCODE register contains
FFFFFFFFh.
XC18V00 TAP Characteristics
The XC18V00 family performs both in-system programming and IEEE 1149.1 Boundary-Scan (JTAG) testing via a single
four-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform
both functions. The AC characteristics of the XC18V00 TAP are described as follows.
TAP Timing
shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both Boundary-
Scan and ISP operations.
X-Ref Target - Figure 4
T
CKMIN1,2
TCK
T
MSS
T
MSH
TMS
T
DIS
T
DIH
TDI
T
DOV
TDO
DS026_04_032702
Figure 4:
Test Access Port Timing
TAP AC Parameters
shows the timing parameters for the TAP waveforms shown in
Table 6:
Test Access Port Timing Parameters
Symbol
T
CKMIN1
T
CKMIN2
T
MSS
T
MSH
T
DIS
T
DIH
T
DOV
Parameter
TCK minimum clock period
TCK minimum clock period, Bypass mode
TMS setup time
TMS hold time
TDI setup time
TDI hold time
TDO valid delay
Min
100
50
10
25
10
25
Max
25
Units
ns
ns
ns
ns
ns
ns
ns
DS026 (v5.2) January 11, 2008
Product Specification
8