R
XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 5
(2)
CCO
V
(1)
V
V
CCO CCINT
(1)
V
V
D0
DIN
MODE PINS
CCINT
(2)
CCO
DIN
CCLK
...OPTIONAL
Slave FPGAs
with identical
configurations
Xilinx FPGA
Master Serial
XC18V00
PROM
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
CLK
CE
CCLK
DONE
...OPTIONAL
Daisy-chained
Slave FPGAs
with different
configurations
CEO
DOUT
DOUT
CCLK
OE/RESET
CF
INIT_B (INIT)
TDI
TMS
TCK
TDO
TDI
PROG_B (PROGRAM)
DONE
TMS
TCK
INIT_B (INIT)
PROG_B (PROGRAM)
TDO
TDI
GND
TMS
TCK
TDO
GND
Notes:
1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
2 For compatible voltages, refer to the appropriate data sheet.
ds026_18_20051007
Figure 5: Master Serial Mode
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
10
XILINX [ XILINX, INC ]
