R
XC18V00 Series In-System-Programmable Configuration PROMs
X-Ref Target - Figure 6
(2)
CCO
V
External
(3)
Oscillator
(1)
8
V
CCO
V
CCINT
(1)
V
D[0:7]
D[0:7]
MODE PINS
RDWR_B
CS_B
CCINT
(2)
V
CCO
Xilinx FPGA
SelectMAP or
Slave-Parallel
XC18V00
PROM
CLK
CE
CCLK
TDI
TMS
TCK
TDO
DONE
CEO
D[0:7]
CCLK
OE/RESET
CF
INIT_B (INIT)
...OPTIONAL
Slave FPGAs
with identical
configurations
PROG_B (PROGRAM)
DONE
TDO
TDI
INIT_B (INIT)
PROG_B (PROGRAM)
TMS
GND
TCK
TDO
GND
Notes:
1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
2 For compatible voltages, refer to the appropriate data sheet.
3 External oscillator required for Virtex/Virtex-E SelectMAP, for Virtex-II/Virtex-II Pro Slave SelectMAP, and for
Spartan-II/Spartan-IIE Slave-Parallel modes.
DS026_19_111207
Figure 6: Master/Slave SelectMAP Mode or Slave Parallel Mode
DS026 (v5.2) January 11, 2008
www.xilinx.com
Product Specification
11
XILINX [ XILINX, INC ]
