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XC18V01VQ44C0936 参数 Datasheet PDF下载

XC18V01VQ44C0936图片预览
型号: XC18V01VQ44C0936
PDF下载: 下载PDF文件 查看货源
内容描述: [Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44]
分类和应用: 内存集成电路
文件页数/大小: 24 页 / 316 K
品牌: XILINX [ XILINX, INC ]
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R
XC18V00 Series In-System-Programmable Configuration PROMs
Table 1:
Pin Names and Descriptions
(Cont’d)
Pin
Name
CEO
Boundary-
Scan Order
12
11
Function
DATA OUT
OUTPUT
ENABLE
Pin Description
Chip Enable Output (CEO) is connected to the
CE input of the next PROM in the chain. This
output is Low when CE is Low and OE/RESET
input is High, AND the internal address counter
has been incremented beyond its Terminal
Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
GND is the ground connection.
44-pin VQFP
21
44-pin
PLCC
27
20-pin
SOIC &
PLCC
13
GND
TMS
MODE
SELECT
6, 18, 28 & 41
5
3, 12, 24 &
34
11
11
5
The state of TMS on the rising edge of TCK
determines the state transitions at the Test
Access Port (TAP) controller. TMS has an
internal 50 kΩ resistive pull-up to provide a
logic 1 to the device if the pin is not driven.
This pin is the JTAG test clock. It sequences
the TAP controller and all the JTAG test and
programming electronics.
This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50 kΩ resistive pull-up to provide a
logic 1 to the device if the pin is not driven.
This pin is the serial output for all JTAG
instruction and data registers. TDO has an
internal 50 kΩ resistive pull-up to provide a
logic 1 to the system if the pin is not driven.
Positive 3.3V supply voltage for internal logic.
Positive 3.3V or 2.5V supply voltage connected
to the input buffers
(2)
and output voltage
drivers.
No connects.
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT
31
37
17
V
CCINT
V
CCO
17, 35 & 38
(3)
23, 41 &
44
(3)
18 & 20
(3)
19
8, 16, 26 & 36 14, 22, 32 &
42
1, 2, 4,
11, 12, 20, 22,
23, 24, 30, 32,
33, 34, 37, 39,
44
1, 6, 7, 8,
10, 17, 18,
26, 28, 29,
30, 36, 38,
39, 40, 43
NC
Notes:
1.
2.
3.
By default, pin 7 is the D4 pin in the 20-pin packages. However, CF
D4 programming option can be set to override the default and route
the CF function to pin 7 in the Serial mode.
For devices with IDCODES
0502x093h,
the input buffers are supplied by V
CCINT
.
For devices with IDCODES
0503x093h,
the following V
CCINT
pins are no-connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC
package, and pin 20 in 20-pin SOIC and 20-pin PLCC packages.
DS026 (v5.2) January 11, 2008
Product Specification
3