R
XC17V00 Series Configuration PROM
OPTIONAL
Daisy-chained
FPGAs with
different
DOUT
configurations
FPGA
OPTIONAL
V
CC
Slave FPGAs
with identical
configurations
4.7K
Modes*
Vcco
Vcc
V
CC
**
V
V
BUSY
DATA
CC CCO
DATA
DIN
BUSY
First
PROM
CCLK
Cascaded
PROM
CLK
CE
CLK
CE
CEO
DONE
INIT
OE/RESET
OE/RESET
PROGRAM
(Low Resets the Address Pointer)
*For Mode pin connections, refer to the appropriate FPGA data sheet.
**Virtex, Virtex-E is 300 ohms, all others are 4.7K.
Master Serial Mode
I/O*
I/O*
V
CC
V
CCO
CS
Modes***
WRITE
External Osc
3.3V
4.7K
1K
1K
VIRTEX
Select MAP
V
CC
V
CCO
V
CC
BUSY
XC17Vxx
BUSY
**
CLK
CCLK
8
CEO
D[0:7]
DONE
INIT
D[0:7]
CE
OE/RESET
*CS and WRITE must be pulled down to be used as I/O. One option is shown.
**Virtex, Virtex-E is 300 ohms, all others are 4.7K.
***For Mode pin connections, refer to the appropriate FPGA data sheet.
Virtex Select MAP Mode, XC17V16 and XC17V08 only.
DS073_03_072600
Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode
(dotted lines indicates optional connection)
6
www.xilinx.com
DS073 (v1.0) July 26, 2000
1-800-255-7778
Advance Product Specification
XILINX [ XILINX, INC ]
