OPB 16450 UART
Line Control Register
As shown in Table 9, the Line Control Register contains the serial communication configuration bits.
Table 9: Line Control Register Bit Definitions
Bit
Location
Name
Access
Reset Value
Description
Divisor Latch Access Bit.
7
DLAB
Read/Write
“0”
"1" -> Allows access to the Divisor Latch Registers
and reading of the FIFO Control Register.
6
5
4
Set Break
Stick Parity
EPS
Read/Write
Read/Write
Read/Write
“0”
“0”
“0”
Set Break.
"1" -> Sets SOUT to "0".
Stick Parity.
"1" -> Forces parity to "1" or "0" based on bits 3 and 4.
Even Parity Select.
1 -> Selects Even parity.
0-> Selects Odd parity.
Parity Enable.
3
2
PEN
STB
Read/Write
Read/Write
“0”
“0”
"1" -> Enables parity.
Number of Stop Bits.
"0" -> 1 Stop bit.
"1" -> 2 Stop bits or 1.5 if
5 bits/character selected).
Word Length Select.
"00" -> 5 bits/character.
"01" -> 6 bits/character.
"10" -> 7 bits/character.
"11" -> 8 bits/character.
1-0
WLS
Read/Write
“00”
Modem Control Register
As shown in Table 10, the Modem Control Register contains the modem signaling configuration bits.
(1)
Table 10: Modem Control Register Bit Definitions
Bit
Location
Name
Loop
Out2
Access
Reset Value
“000"
Description
7-5
4
Read/Write
Read/Write
"0"
Loop Back.
"1" -> Enables loop back.
User Output 2.
3
Read/Write
"0"
"1" -> Drives OUT2N low.
"0" -> Drives OUT2N high.
DS433 August 18, 2004
Product Specification
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9
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