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DS635 参数 Datasheet PDF下载

DS635图片预览
型号: DS635
PDF下载: 下载PDF文件 查看货源
内容描述: 了XA Spartan -3E汽车FPGA系列数据手册 [XA Spartan-3E Automotive FPGA Family Data Sheet]
分类和应用:
文件页数/大小: 37 页 / 723 K
品牌: XILINX [ XILINX, INC ]
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R
Revision History  
The following table shows the revision history for this document.  
Date  
Version  
1.0  
Revision  
08/31/07  
01/20/09  
Initial Xilinx release.  
Updated "Key Feature Differences from Commercial XC Devices."  
Updated T requirement in Table 43.  
1.1  
ACC  
Updated description of T  
and T  
in Table 42.  
DCC  
CCD  
Removed Table 45: MultiBoot Trigger Timing.  
09/09/09  
2.0  
Added package sizes to Table 2, page 4.  
Removed Genealogy Viewer Link from "Package Marking," page 5.  
Updated data and notes for Table 6, page 8.  
Updated test conditions for R and maximum value for C in Table 7, page 8.  
PU  
IN  
Updated notes for Table 8, page 9.  
Updated Max V  
for LVTTL and LVCMOS33, removed PCIX data, updated V Max for  
CCO  
IL  
LVCMOS18, LVCMOS15, and LVCMOS12, updated V Min for LVCMOS12, and added  
IH  
note 6 in Table 9, page 11.  
Removed PCIX data, revised note 2, and added note 4 in Table 10, page 12.  
Updated figure description of Figure 5, page 14.  
Added note 4 to Table 13, page 14.  
Removed PC166_3 and PCIX adjustment values from Table 17, page 17.  
Deleted Table 18 (duplicate of Table 17, page 17). Subsequent tables renumbered.  
Removed PCIX data Table 18, page 18.  
Removed PCIX data and removed V  
values for DIFF_HSTL_I_18,  
DIFF_HSTL_III_18, DIFF_SSTL18_I, and DIFF_SSTL2_I from Table 19, page 19.  
REF  
Updated T minimum setup time in Table 20, page 20.  
DICK  
Updated notes, references to notes, and revised the maximum clock-to-output times for  
Table 24, page 22.  
T
MSCKP_P  
Added "Spread Spectrum," page 24.  
Updated note 3 in Table 26, page 25.  
Added note 4 Table 28, page 26.  
Updated notes, references to notes, and CLKOUT_PER_JITT_FX data in Table 29,  
page 27.  
Updated MAX_STEPS data in Table 31, page 28.  
Updated ConfigRate Setting for T  
to indicate 1 is the default value in Table 34,  
CCLK1  
page 30.  
Updated ConfigRate Setting for F  
to indicate 1 is the default value in Table 35,  
CCLK1  
page 30.  
Notice of Disclaimer  
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND  
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED  
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE  
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.  
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE  
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES  
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO  
APPLICABLE LAWS AND REGULATIONS.  
DS635 (v2.0) September 9, 2009  
www.xilinx.com  
Product Specification  
36  
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