R
Master Serial and Slave Serial Mode Timing
Table 38: Timing for the Master Serial and Slave Serial Configuration Modes
-4 Speed Grade
Slave/
Symbol
Description
Master
Min
Max
Units
Clock-to-Output Times
T
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
Both
Both
Both
1.5
10.0
ns
CCO
Setup Times
T
The time from the setup of data at the DIN pin to the active edge of
the CCLK pin
11.0
0
-
-
ns
ns
DCC
Hold Times
T
The time from the active edge of the CCLK pin to the point when
data is last held at the DIN pin
CCD
Clock Timing
T
T
F
High pulse width at the CCLK input pin
Master
Slave
Master
Slave
Slave
See Table 36
See Table 37
See Table 36
See Table 37
CCH
Low pulse width at the CCLK input pin
CCL
(2)
Frequency of the clock signal at
the CCLK input pin
No bitstream compression
With bitstream compression
0
0
66
MHz
MHz
CCSER
20
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
31
XILINX [ XILINX, INC ]
