R
IEEE 1149.1/1553 JTAG Test Access Port Timing
Table 44: Timing for the JTAG Test Access Port
-4 Speed Grade
Symbol
Description
Min
Max
Units
Clock-to-Output Times
T
The time from the falling transition on the TCK pin
to data appearing at the TDO pin
1.0
11.0
ns
TCKTDO
Setup Times
T
The time from the setup of data at the TDI pin to
the rising transition at the TCK pin
7.0
7.0
-
-
ns
ns
TDITCK
T
The time from the setup of a logic level at the TMS
pin to the rising transition at the TCK pin
TMSTCK
Hold Times
T
The time from the rising transition at the TCK pin
to the point when data is last held at the TDI pin
0
0
-
-
ns
ns
TCKTDI
T
The time from the rising transition at the TCK pin
to the point when a logic level is last held at the
TMS pin
TCKTMS
Clock Timing
T
T
F
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
5
5
-
-
-
ns
ns
CCH
CCL
TCK
25
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6.
DS635 (v2.0) September 9, 2009
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