R
Configuration and JTAG Timing
Table 33: Power-On Timing and the Beginning of Configuration
-4 Speed Grade
Symbol
(2)
Description
Device
Min
Max
5
Units
ms
ms
ms
ms
ms
μs
TPOR
The time from the application of VCCINT, VCCAUX, and VCCO XA3S100E
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
XA3S500E
-
XA3S250E
-
5
-
5
XA3S1200E
XA3S1600E
-
5
-
7
TPROG
The width of the low-going pulse on the PROG_B pin
All
0.5
-
(2)
TPL
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
All
-
0.5
0.5
1
ms
ms
ms
ms
ms
ns
-
-
-
2
-
2
TINIT
Minimum Low pulse width on INIT_B output
250
0.5
-
(3)
TICCK
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All
4.0
μs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6. This means power must be applied to all V
, V
,
CCINT CCO
and V
lines.
CCAUX
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
DS635 (v2.0) September 9, 2009
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Product Specification
29
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