R
Serial Peripheral Interface Configuration Timing
Table 40: Timing for SPI Configuration Mode
Symbol
Description
Minimum
Maximum
(see Table 34)
(see Table 34)
-
Units
T
T
T
Initial CCLK clock period
CCLK1
CCLKn
MINIT
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] and M[2:0] mode pins before the rising
edge of INIT_B
50
0
ns
ns
T
Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of
INIT_B
-
INITM
T
T
T
MOSI output valid after CCLK edge
See Table 38
See Table 38
See Table 38
CCO
DCC
CCD
Setup time on DIN data input before CCLK edge
Hold time on DIN data input after CCLK edge
Table 41: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol
Description
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
Requirement
Units
ns
T
TCCS ≤ TMCCL1 – TCCO
TDSU ≤ TMCCL1 – TCCO
CCS
DSU
T
ns
T
SPI serial Flash PROM data input hold time
ns
ns
DH
V
TDH ≤ TMCCH1
T
SPI serial Flash PROM data clock-to-output time
TV ≤ TMCCLn – TDCC
f or f
Maximum SPI serial Flash PROM clock frequency (also depends
on specific read command used)
MHz
C
R
1
------------------------------
fC ≥
TCCLKn(min)
Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
33
XILINX [ XILINX, INC ]
