R
Byte Peripheral Interface Configuration Timing
Table 42: Timing for BPI Configuration Mode
Symbol
Description
Minimum Maximum
(see Table 34)
Units
T
Initial CCLK clock period
CCLK1
CCLKn
MINIT
T
T
CCLK clock period after FPGA loads ConfigRate setting
(see Table 34)
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising
edge of INIT_B
50
0
-
ns
ns
T
T
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising
edge of INIT_B
-
INITM
BPI-UP:
(M[2:0]=<0:1:0>)
Minimum period of initial A[23:0] address cycle;
LDC[2:0] and HDC are asserted and valid
5
2
5
2
T
CCLK1
cycles
INITADDR
BPI-DN:
(M[2:0]=<0:1:1>)
T
T
T
Address A[23:0] outputs valid after CCLK falling edge
See Table 38
See Table 38
See Table 38
CCO
DCC
CCD
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
Table 43: Configuration Timing Requirements for Attached Parallel NOR Flash
Symbol
Description
Requirement
Units
T
Parallel NOR Flash PROM chip-select
time
CE
TCE ≤ TINITADDR
TOE ≤ TINITADDR
TACC ≤ 0.5TCCLKn(min) – TCCO – TDCC – PCB
ns
(t
)
ELQV
T
Parallel NOR Flash PROM
output-enable time
OE
ns
ns
(t
)
)
GLQV
T
Parallel NOR Flash PROM read access
time
ACC
(t
AVQV
T
(t
BYTE
For x8/x16 PROMs only: BYTE# to
output valid time
TBYTE ≤ TINITADDR
ns
(3)
FLQV,
t
)
FHQV
Notes:
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s HSWAP pin is High or Low.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
34
XILINX [ XILINX, INC ]
