R
Table 31: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Phase Shifting Range
MAX_STEPS(2)
Description
Units
Maximum allowed number of DCM_DELAY_STEP
steps for a given CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double the clock
effective clock period.
CLKIN < 60 MHz
CLKIN > 60 MHz
[INTEGER(10 • steps
(TCLKIN – 3 ns))]
[INTEGER(15 • steps
(TCLKIN – 3 ns))]
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
[MAX_STEPS •
DCM_DELAY_STEP_MIN]
ns
ns
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
[MAX_STEPS •
DCM_DELAY_STEP_MAX]
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 30.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT
attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 27.
Miscellaneous DCM Timing
Table 32: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
(1)
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
-
CLKIN
cycles
(2)
DCM_RST_PW_MAX
Maximum duration of a RST pulse width
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
seconds
seconds
minutes
minutes
(3)
DCM_CONFIG_LAG_TIME
Maximum duration from V
applied to FPGA
CCINT
configuration successfully completed (DONE pin goes
High) and clocks applied to DCM DLL
Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2. This specification is equivalent to the Virtex-4 DCM_RESET specification. This specification does not apply for Spartan-3E FPGAs.
3. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
28
XILINX [ XILINX, INC ]
