R
Platform Flash XL High-Density Configuration and Storage Device
Bus Operations
There are six standard bus operations that control the
device: Bus Read, Bus Write, Address Latch, Output
Disable, Standby and Reset (Table 5).
Address Latch
Address latch operations input valid addresses. Both Chip
enable and Latch Enable must be at V during address
IL
latch operations. Addresses are latched on the rising edge
of Latch Enable.
Bus Read
Bus Read operations are used to output the contents of the
Memory Array, Electronic Signature, Status Register and
Common Flash Interface. Both Chip Enable and Output
Output Disable
The outputs are held at high impedance when Output
Enable must be at V in order to perform a read operation.
IL
Enable is at V .
The Chip Enable input should be used to enable the device.
Output Enable should be used to gate data onto the output.
The data read depends on the previous command written to
the memory (see “Command Interface,” page 14).
IH
Standby
Standby disables most of the internal circuitry allowing a
substantial reduction of the current consumption. The
memory is in standby when Chip Enable and Reset are at
Bus Write
V . Power consumption is reduced to the standby level
Bus Write operations write commands to the memory or
latch Input Data to be programmed. A Bus Write operation
IH
I
, and the outputs are set to high impedance
DD3
independently from Output Enable or Write Enable. If Chip
is initiated when Chip Enable and Write Enable are at V
IL
Enable switches to V during a program or erase operation,
with Output Enable at V . Commands, Input Data and
IH
IH
the device enters Standby mode when finished with the
program or erase operation.
Addresses are latched on the rising edge of Write Enable or
Chip Enable, whichever occurs first. The addresses can be
latched prior to the write operation by toggling Latch Enable
Reset
(when Chip Enable is at V ).
IL
The Latch Enable signal can also be held at V by the
system, but then the system must guarantee that the
During Reset mode, the memory is deselected and the
outputs are high impedance. The memory is in Reset mode
IL
address lines remain stable for at least T
.
when Reset is at V . Power consumption is reduced to the
WHAX
IL
Reset level independently from Chip Enable, Output Enable
Note: Typically glitches of less than 5 ns on Chip Enable or
Write Enable are ignored by the memory and do not affect Bus
Write operations.
or Write Enable. If Reset is pulled to V during a Program
SS
or Erase, this operation is aborted and the memory content
is no longer valid.
(1)
Table 5: Bus Operations
READY_WAIT(2,3)
DQ15-DQ0
Operation
E
G
W
L
RP
CR4 = 1
CR4 = 0
(4)
(4)
Bus Read
Bus Write
Address Latch
Output Disable
Standby
VIL
VIL
VIL
VIL
VIH
X
VIL VIH VIL
VIH VIL VIL
VIH
VIH
VIH
VIH
VIH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
–
–
Data output
Data input
Data output or Hi-Z(5)
Hi-Z
X
VIH
VIL
–
VIH VIH
X
X
Hi-Z
Hi-Z
–
X
X
X
X
Hi-Z
(6)
(7)
Reset
X
VIL
VIH
VIL
Hi-Z
FALS
VIL
VIL VIH
VIH
Hi-Z
–
Data output
Notes:
1. X = Don't care.
2. If READY_WAIT is configured as an output wait signal (CR4 = 0), then the CR10 Configuration Register bit defines the signal polarity.
3. READY_WAIT is configured using the CR4 Configuration Register bit.
4. L can be tied to V if the valid address was previously latched.
IH
5. Depends on G.
6. The Configuration Register reverts to its default value after a Low logic level (V ) is detected on the RP pin.
IL
7. READY_WAIT pin used as an output. READY_WAIT goes Low T
after RP goes Low.
PLRWL
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
11
XILINX [ XILINX, INC ]
