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DS617 参数 Datasheet PDF下载

DS617图片预览
型号: DS617
PDF下载: 下载PDF文件 查看货源
内容描述: 平台的Flash XL高密度配置和存储设备 [Platform Flash XL High-Density Configuration and Storage Device]
分类和应用: 存储
文件页数/大小: 88 页 / 2352 K
品牌: XILINX [ XILINX, INC ]
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R
Platform Flash XL High-Density Configuration and Storage Device  
into Read Electronic Signature mode. Subsequent Bus  
Read cycles output Electronic Signature data, and the  
Program/Erase controller continues to program or erase in  
the background.  
If the block is protected, then the erase operation aborts,  
data in the block is not changed, and the Status Register  
outputs the error.  
Two Bus Write cycles are required to issue the command.  
The Read Electronic Signature command only changes the  
read mode of the addressed bank. The read modes of other  
banks are not affected. Only Asynchronous Read and  
Single Synchronous Read operations should be used to  
read the Electronic Signature. A Read Array command is  
required to return the bank to Read Array mode.  
The first bus cycle sets up the Block Erase command.  
The second latches the block address and starts the  
Program/Erase Controller.  
If the second bus cycle is not the Block Erase Confirm code,  
Status Register bits SR4 and SR5 are set and the  
command is aborted.  
Read CFI Query Command  
After the command is issued, the bank enters Read Status  
Register mode, and any read operation within the  
addressed bank outputs the contents of the Status Register.  
A Read Array command is required to return the bank to  
Read Array mode.  
The Read CFI Query command is used to read data from  
the Common Flash Interface (CFI). One Bus Write cycle is  
required to issue the Read CFI Query command. After a  
bank is in Read CFI Query mode, subsequent Bus Read  
operations in the same bank read from the Common Flash  
Interface. The Read CFI Query command can be issued at  
any time, even during program or erase operations.  
During Block Erase operations, the bank containing the  
block being erased only accepts the Read Array, Read  
Status Register, Read Electronic Signature, Read CFI  
Query, and Program/Erase Suspend command; all other  
commands are ignored.  
If a Read CFI Query command is issued to a bank executing  
a program or erase operation, the bank enters into Read  
CFI Query mode. Subsequent Bus Read cycles output CFI  
data, and the Program/Erase controller continues to  
program or erase in the background.  
The Block Erase operation aborts if Reset (RP) goes to V .  
As data integrity cannot be guaranteed when the Block  
Erase operation is aborted, the block must be erased again.  
IL  
The Read CFI Query command only changes the read  
mode of the addressed bank. The read modes of other  
banks are not affected. Only Asynchronous Read and  
Single Synchronous Read operations should be used to  
read from the CFI. A Read Array command is required to  
return the bank to Read Array mode. Dual operations  
between the Parameter Bank and the CFI memory space  
are not allowed (see Table 17, page 36 for details).  
Refer to "Dual Operations and Multiple Bank Architecture,"  
page 35 for detailed information about simultaneous  
operations allowed in banks not being erased.  
Typical Erase times are given in Table 21, page 44.  
See Figure 41, page 75, for a suggested flowchart for using  
the Block Erase command.  
See "Appendix B: Common Flash Interface," page 65,  
Table 36, page 65, through Table 45, page 70, Table 38,  
Table 38 for details on the information contained in the  
Common Flash Interface memory area.  
Blank Check Command  
The Blank Check command is used to check whether a Block  
is completely erased. Only one block at a time can be  
checked. To use the Blank Check command, V must be  
PP  
equal to V  
. If V is not equal to V  
, the device ignores  
PPH  
PP  
PPH  
Clear Status Register Command  
the command and no error is shown in the Status Register.  
The Clear Status Register command can be used to reset  
(set to ‘0’) all error bits (SR1, 3, 4 and 5) in the Status  
Register. One Bus Write cycle is required to issue the Clear  
Status Register command. The Clear Status Register  
command does not affect the read mode of the bank.  
Two bus cycles are required to issue the Blank Check  
command:  
The first bus cycle writes the Blank Check command  
(BCh) to any address in the block to be checked.  
The second bus cycle writes the Blank Check Confirm  
command (CBh) to any address in the block to be  
checked and starts the Blank Check operation.  
The error bits in the Status Register do not automatically  
return to ‘0’ when a new command is issued. The error bits  
in the Status Register should be cleared before attempting a  
new program or erase command.  
If the second bus cycle is not Blank Check Confirm,  
Status Register bits SR4 and SR5 are set to '1', and the  
command aborts.  
Block Erase Command  
The Block Erase command is used to erase a block. It sets  
all the bits within the selected block to ‘1’. All previous data  
in the block is lost.  
After the command is issued, the addressed bank  
automatically enters the Status Register mode and further  
reads within the bank output the Status Register contents.  
DS617 (v3.0.1) January 07, 2010  
www.xilinx.com  
Product Specification  
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