R
Platform Flash XL High-Density Configuration and Storage Device
The only operation permitted during Blank Check is Read
Status Register. Dual Operations are not supported while a
Blank Check operation is in progress. Blank Check
operations cannot be suspended and are not allowed while
the device is in Program/Erase Suspend.
Buffer Program Command
The Buffer Program Command makes use of the device’s
32-word Write Buffer to speed up programming. Up to 32
words can be loaded into the Write Buffer. The Buffer
Program command dramatically reduces in-system
programming time compared to the standard non-buffered
Program command.
The SR7 Status Register bit indicates the status of the
Blank Check operation in progress:
•
SR7 = '0' indicates that the Blank Check operation is
still ongoing.
Four successive steps are required to issue the Buffer
Program command:
•
SR7 = '1' indicates that the operation is complete.
1. The first Bus Write cycle sets up the Buffer Program
command. The setup code can be addressed to any
location within the targeted block.
The SR5 Status Register bit goes High (SR5 = '1') to
indicate that the Blank Check operation has failed.
At the end of the operation the bank remains in the Read
Status Register mode until another command is written to
the Command Interface.
After the first Bus Write cycle, read operations in the
bank output the contents of the Status Register. Status
Register bit SR7 should be read to check that the buffer
is available (SR7 = 1). If the buffer is not available (SR7
= 0), the Buffer Program command must be re-issued to
update the Status Register contents.
See Figure 38, page 72, for a suggested flowchart for using
the Blank Check command.
Typical Blank Check times are given in Table 21, page 44.
2. The second Bus Write cycle sets up the number of
words to be programmed. Value n is written to the same
block address, where n + 1 is the number of words to be
programmed.
Program Command
The program command is used to program a single word to the
memory array. If the block being programmed is protected,
then the Program operation aborts, data in the block is not
changed, and the Status Register outputs the error.
3. A total of n + 1 Bus Write cycles are used to load the
address and data for each word into the Write Buffer.
Addresses must lie within the range from the start
address to the start address + n, where the start
address is the location of the first data to be
Two Bus Write cycles are required to issue the Program
Command.
programmed. Optimum performance is obtained when
the start address corresponds to a 32-word boundary.
•
•
The first bus cycle sets up the Program command.
The second latches the address and data to be
programmed and starts the Program/Erase Controller.
4. The final Bus Write cycle confirms the Buffer Program
command and starts the program operation.
After the programming starts, read operations in the bank
being programmed output the Status Register content.
All the addresses used in the Buffer Program operation
must lie within the same block. Invalid address
combinations or failing to follow the correct sequence of Bus
Write cycles sets an error in the Status Register and aborts
the operation without affecting the data in the memory array.
During a Program operation, the bank containing the word
being programmed only accepts the Read Array, Read
Status Register, Read Electronic Signature, Read CFI
Query and Program/Erase Suspend command; all other
commands are ignored. A Read Array command is required
to return the bank to Read Array mode.
If the block being programmed is protected, an error is set in
the Status Register, and the operation aborts without
affecting the data in the memory array.
Refer to "Dual Operations and Multiple Bank Architecture,"
page 35 for detailed information about simultaneous
operations allowed in banks not being programmed.
During Buffer Program operations, the bank being
programmed only accepts the Read Array, Read Status
Register, Read Electronic Signature, Read CFI Query and
Program/Erase Suspend command; all other commands
are ignored.
Typical Program times are given in Table 21, page 44.
The Program operation aborts if Reset (RP) goes to V . As
IL
data integrity cannot be guaranteed when the Program
operation is aborted, the word must be reprogrammed.
Refer to "Dual Operations and Multiple Bank Architecture,"
page 35 for detailed information about simultaneous
operations allowed in banks not being programmed.
See Figure 37, page 71, for the flowchart for using the
Program command.
See Figure 39, page 73, for a suggested flowchart on using
the Buffer Program command.
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
14
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