R
Platform Flash XL High-Density Configuration and Storage Device
the READY_WAIT signal to a valid input High). The device
waits until the READY_WAIT input becomes a valid input
High before permitting a synchronous read or accepting a
command. Connecting the READY_WAIT to the FPGA
INIT_B pin in a wired-and circuit creates a handshake
coordinating the initiation of the device synchronous read
with the start of the FPGA configuration sequence.
Latch Enable (L)
Latch Enable latches the address bits on its rising edge.
The address latch is transparent when Latch Enable is at
V and inhibited when Latch Enable is at V .
IL
IH
The Latch Enable (L) signal must be held at V during the
power-up phase, during the FALS restart phase and
through the entire FALS.
IH
When READY_WAIT is an input/open-drain ready signal, the
system can drive READY_WAIT to V to reinitiate a
synchronous read operation. A valid address must be provided
to the device for a reinitiated synchronous read operation.
IL
In asynchronous mode, the address is latched on L going
High. or addresses are sent continuously if L is held Low.
During Write operations, L can be tied Low (V ) to allow the
IL
addresses to flow through.
Optionally, READY_WAIT can be configured as an output
signaling a wait condition during a synchronous read
operation. The wait condition indicates a clock cycle during
which the output data is not valid. When configured as an
output wait signal, READY_WAIT is high impedance when
Table 3: Latch Enable Logic Levels in Synchronous
and Asynchronous Modes
Operation
Bus Read
Bus Write
Address Latch
Standby
Asynchronous
Synchronous
Chip Enable is at V or Output Enable is at V . Only when
IH
IH
X
X or toggling
Toggling
X
VIH
X or toggling
Toggling
X
configured as a wait signal, READY_WAIT can be configured
to be active during the wait cycle or one clock cycle in
advance, and the READY_WAIT polarity can be configured.
VDD Supply Voltage
Reset
VIH
VIH
V
provides the power supply to the internal core of the
DD
FALS
VIH
VIH
memory device and is the main power supply for all
operations (Read, Program and Erase).
Power-up
VIH
VIH
Notes:
VDDQ Supply Voltage
1. See waveforms in the "DC and AC Parameters" section for
details.
V
provides the power supply to the I/O pins and enables
DDQ
all outputs to be powered independently of V
.
DD
Clock (K)
VPP Program Supply Voltage
The Clock input synchronizes the memory to the FPGA
during synchronous read operations. The address is
latched on a Clock edge (rising or falling, according to the
V
is either a control input or a power supply pin, selected
PP
by the voltage range applied to the pin.
configuration settings) when Latch Enable is at V . Clock is
ignored during asynchronous read and in write operations.
IL
If V is kept in a low voltage range (0V to V
), V is
PP
DDQ
PP
seen as a control input. In this case a voltage lower than
gives absolute protection against program or erase,
V
PPLK
Ready/Wait (READY_WAIT)
while V in the V
range enables these functions. V is
PP
PP1
PP
only sampled at the beginning of a program or erase — a
change in its value after the operation starts does not have
any effect, and all program or erase operations continue.
Caution! The READY_WAIT requires an external pull-up
resistor to VDDQ. The external pull-up resistor must be
sufficiently strong to ensure a clean, Low-to-High transition
within less than one microsecond (TRWRT) when the
READY_WAIT pin is released to a high-impedance state.
If V is in the range of V
, the signal acts as a power
PP
PPH
supply pin. In this condition V must be stable until the
PP
READY_WAIT can perform one of two functions. By default,
READY_WAIT is an input/open-drain ready signal
coordinating the initiation of the device's synchronous read
operation with the start of an FPGA configuration sequence.
Optionally, READY_WAIT can be dynamically configured as
an output wait signal, indicating a wait condition during a
synchronous read operation.
Program/Erase algorithm is completed.
VSS Ground
V
Ground is the reference for the core supply and must
SS
be connected to the system ground.
VSSQ Ground
Upon a power-on reset (POR) or RP-pin reset event, the
V
Ground is the reference for the input/output circuitry
SSQ
device drives READY_WAIT to V until the device is ready to
IL
driven by V
. V
must be connected to V
.
DDQ
SSQ
SS
initiate a synchronous read or receive a command. When the
device reaches an internal ready state from a reset condition,
READY_WAIT is released to a high-impedance state (an
Note: Each device in a system should have VDD, VDDQ and VPP
decoupled with a 0.1 μF ceramic capacitor close to the pin (high-
frequency, inherently low-inductance capacitors should be placed
external pull-up resistor to V
is required to externally pull
DDQ
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
7
XILINX [ XILINX, INC ]
