R
Functional Description
Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
CCLK
Output
Configuration Clock. Generated Not used in single FPGA
User I/O. If bitstream
by FPGA internal oscillator.
Frequency controlled by
applications but actively drives. In option Persist=Yes,
a daisy-chain configuration, drives becomes part of
ConfigRate bitstream generator
the CCLK inputs of all other
SelectMap parallel
peripheral interface.
option. If CCLK PCB trace is long or FPGAs in the daisy-chain.
hasmultipleconnections, terminate
this output to maintain signal
integrity. See CCLK Design
Considerations.
INIT_B
Open-drain
Initialization Indicator. Active
Active during configuration. If CRC User I/O. If unused in the
bidirectional I/O Low. Goes Low at start of
configuration during the
error detected during
configuration, FPGA drives
INIT_B Low.
application, drive INIT_B
High.
Initialization memory clearing
process. Released at the end of
memory clearing, when the mode
select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
DONE
Open-drain
FPGA Configuration Done. Low
Low indicates that the FPGA is not Pulled High via external
bidirectional I/O during configuration. Goes High
when FPGA successfully
yet configured.
pull-up. When High,
indicates that the FPGA is
successfully configured.
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
PROG_B
Input
Program FPGA. Active Low. When Must be High to allow
asserted Low for 500 ns or longer, configuration to start.
forces the FPGA to restart its
configuration process by clearing
configuration memory and
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
resetting the DONE and INIT_B
programming access to
Flash PROM pins.
pins once PROG_B returns High.
Recommend external 4.7 kΩ
pull-up resistor to 2.5V. Internal
pull-up value may be weaker (see
Table 78). If driving externally with
a 3.3V output, use an open-drain or
open-collector driver or use a
current limiting series resistor.
The PROM supply voltage also connects to the FPGA’s
VCCO_2 supply input. In many systems, the PROM supply
feeding the FPGA’s VCCO_2 input is valid before the
Voltage Compatibility
V
The FPGA’s parallel Flash interface signals are within
I/O Banks 1 and 2. The majority of parallel Flash PROMs
use a single 3.3V supply voltage. Consequently, in most
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages
must also be 3.3V to match the parallel Flash PROM. There
are some 1.8V parallel Flash PROMs available and the
FPGA interfaces with these devices if the VCCO_1 and
VCCO_2 supplies are also 1.8V.
FPGA’s other V
and V
supplies, and conse-
CCINT
CCAUX
quently, there is no issue. However, if the PROM supply is
last in the sequence, a potential race occurs between the
FPGA and the parallel Flash PROM. See Power-On Pre-
cautions if 3.3V Supply is Last in Sequence for a similar
description of the issue for SPI Flash PROMs.
Supported Parallel NOR Flash PROM Densities
Power-On Precautions if PROM Supply is Last in
Sequence
Table 60 indicates the smallest usable parallel Flash PROM
to program a single Spartan-3E FPGA. Parallel Flash den-
sity is specified in bits but addressed as bytes. The FPGA
presents up to 24 address lines during configuration but not
all are required for single FPGA applications. Table 60
Like SPI Flash PROMs, parallel Flash PROMs typically
require some amount of internal initialization time when the
supply voltage reaches its minimum value.
DS312-2 (v3.8) August 26, 2009
www.xilinx.com
89
Product Specification
XILINX [ XILINX, INC ]
