R
Functional Description
+1.2V
V
VCCINT
HSWAP
VCCO_0
VCCO_0
P
I
VCCO
VCCO_1
LDC0
V
x8 or
CE#
x8/x16
Flash
LDC1
OE#
HDC
WE#
BYTE#
PROM
LDC2
Not available
in VQ100
package
D
A[16:0]
DQ[15:7]
BPI Mode
VCCO_2
D[7:0]
V
‘0’
‘1’
A
M2
M1
M0
DQ[7:0]
A[n:0]
A[23:17]
GND
V
Spartan-3E
BUSY
CCLK
FPGA
‘0’
‘0’
CSI_B
CSO_B
INIT_B
RDWR_B
+2.5V
JTAG
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_49_082009
Figure 58: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
During configuration, the value of the M0 mode pin
A
Table 58: BPI Addressing Control
determines how the FPGA generates addresses, as shown
Table 58. When M0 = 0, the FPGA generates addresses
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA gener-
ates addresses starting at 0xFF_FFFF (all ones) and decre-
ments the address on every falling CCLK edge.
M2
M1
M0 Start Address
Addressing
Incrementing
Decrementing
0
1
0
0
1
0xFF_FFFF
86
www.xilinx.com
DS312-2 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
