R
Functional Description
Table 63: FPGA Connections to Flash PROM with IO15/A-1 Pin (Continued)
Connection to Flash PROM with
IO15/A-1 Pin
x8 Flash PROM Interface After x16 Flash PROM Interface After
FPGA Configuration FPGA Configuration
FPGA Pin
A[23:1]
A0
A[n:0]
A[n:0]
A[n:0]
IO15/A-1
IO15/A-1 is the least-significant IO15/A-1 is the most-significant
address input
IO[7:0]
data line, IO15
IO[7:0]
D[7:0]
IO[7:0]
User I/O
Upper data lines IO[14:8] not
required unless used as x16 Flash
interface after configuration
Upper data lines IO[14:8] not
required
IO[14:8]
Some x8/x16 Flash PROMs have a long setup time require-
ment on the BYTE# signal. For the FPGA to configure cor-
rectly, the PROM must be in x8 mode with BYTE# = 0 at
power-on or when the FPGA’s PROG_B pin is pulsed Low.
If required, extend the BYTE# setup time for a 3.3V PROM
using an external 680 Ω pull-down resistor on the FPGA’s
LDC2 pin or by delaying assertion of the CSI_B select input
to the FPGA.
and last devices must be Spartan-3E or Virtex-5 FPGAs.
The last FPGA in the chain can be from any Xilinx FPGA
family.
BPI Mode Interaction with Right and Bottom Edge
Global Clock Inputs
Some of the BPI mode configuration pins are shared with
global clock inputs along the right and bottom edges of the
device (Bank 1 and Bank 2, respectively). These pins are
not easily reclaimable for clock inputs after configuration,
especially if the FPGA application access the parallel NOR
Flash after configuration. Table 64 summarizes the shared
pins.
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 59. Use BPI mode (M[2:0] = <0:1:0> or
<0:1:1>) for the FPGA connected to the parallel NOR Flash
PROM and Slave Parallel mode (M[2:0] = <1:1:0>) for all
downstream FPGAs in the daisy-chain. If there are more
than two FPGAs in the chain, then last FPGA in the chain
can be from any Xilinx FPGA family. However, all intermedi-
ate FPGAs located in the chain between the first and last
FPGAs must from either the Spartan-3E or Virtex®-5 FPGA
families.
Table 64: Shared BPI Configuration Mode and Global
Buffer Input Pins
Device
Edge
Global Buffer
Input Pin
BPI Mode
Configuration Pin
GCLK0
GCLK2
RDWR_B
D2
GCLK3
D1
After the master FPGA—the FPGA on the left in the dia-
gram—finishes loading its configuration data from the paral-
lel Flash PROM, the master device continues generating
addresses to the Flash PROM and asserts its CSO_B out-
put Low, enabling the next FPGA in the daisy-chain. The
next FPGA then receives parallel configuration data from
the Flash PROM. The master FPGA’s CCLK output syn-
chronizes data capture.
Bottom
GCLK12
GCLK13
GCLK14
GCLK15
RHCLK0
RHCLK1
RHCLK2
RHCLK3
RHCLK4
RHCLK5
RHCLK6
RHCLK7
D7
D6
D4
D3
A10
A9
If HSWAP = 1, an external 4.7kΩ pull-up resistor must be
added on the CSO_B pin. If HSWAP = 0, no external pull-up
is necessary.
A8
A7
Right
Design Note
A6
BPI mode daisy chain software support is available starting
in ISE 8.2i.
A5
A4
http://www.xilinx.com/support/answers/23061.htm
A3
Also, in a multi-FPGA daisy-chain configuration of more
than two devices, all intermediate FPGAs between the first
92
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DS312-2 (v3.8) August 26, 2009
Product Specification
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