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DS312_09 参数 Datasheet PDF下载

DS312_09图片预览
型号: DS312_09
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列:介绍和订购信息 [Spartan-3E FPGA Family: Introduction and Ordering Information]
分类和应用:
文件页数/大小: 233 页 / 5527 K
品牌: XILINX [ XILINX, INC ]
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Functional Description  
but the upper byte in a portion of the PROM remains  
unused. For configuration, the BPI interface does not  
require any specific Flash PROM features, such as boot  
block or a specific sector size.  
Byte-Wide Peripheral Interface (BPI) Parallel  
Flash Mode  
For additional information, refer to the “Master BPI Mode”  
chapter in UG332.  
The BPI interface also functions with Xilinx parallel Platform  
Flash PROMs (XCFxxP), although the FPGA’s address  
lines are left unconnected.  
In  
Byte-wide  
Peripheral  
Interface  
(BPI)  
mode  
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA config-  
ures itself from an industry-standard parallel NOR Flash  
PROM, as illustrated in Figure 58. The FPGA generates up  
to a 24-bit address lines to access an attached parallel  
Flash. Only 20 address lines are generated for Spartan-3E  
FPGAs in the TQ144 package. Similarly, the XC3S100E  
FPGA in the CP132 package only has 20 address lines  
while the XC3S250E and XC3S500E FPGAs in the same  
package have 24 address lines. When using the VQ100  
package, the BPI mode is not available when using parallel  
NOR Flash, but is supported using parallel Platform Flash  
(XCFxxP).  
The BPI interface also works equally wells with other asyn-  
chronous memories that use a similar SRAM-style interface  
such as SRAM, NVRAM, EEPROM, EPROM, or masked  
ROM.  
NAND Flash memory is commonly used in memory cards  
for digital cameras. Spartan-3E FPGAs do not configure  
directly from NAND Flash memories.  
The FPGA’s internal oscillator controls the interface timing  
and the FPGA supplies the clock on the CCLK output pin.  
However, the CCLK signal is not used in single FPGA appli-  
cations. Similarly, the FPGA drives three pins Low during  
configuration (LDC[2:0]) and one pin High during configura-  
tion (HDC) to the PROM’s control inputs.  
The BPI configuration interface is primarily designed for  
standard parallel NOR Flash PROMs and supports both  
byte-wide (x8) and byte-wide/halfword (x8/x16) PROMs.  
The interface functions with halfword-only (x16) PROMs,  
DS312-2 (v3.8) August 26, 2009  
www.xilinx.com  
85  
Product Specification  
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