R
Functional Description
Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
LDC1
Output
PROM Output Enable
Connect to the PROM
output-enable input (OE#). The
FPGA drives this signal Low
throughout configuration.
HDC
Output
Output
PROM Write Enable
PROM Byte Mode
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
User I/O
LDC2
This signal is not used for x8
User I/O. Drive this pin
PROMs. For PROMs with a x8/x16 High after configuration to
data width control, connect to use a x8/x16 PROM in x16
D
PROM byte-mode input (BYTE#). mode.
See Precautions Using x8/x16
Flash PROMs. FPGA drives this
signal Low throughout
configuration.
A[23:0]
Output
Address
Connect to PROM address inputs. User I/O
High-order address lines may not
be available in all packages and
not all may be required. Number of
address lines required depends
on the size of the attached Flash
PROM. FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are
available in TQ144 package.
D[7:0]
Input
Data Input
FPGA receives byte-wide data on User I/O. If bitstream
these pins in response the
option Persist=Yes,
address presented on A[23:0].
becomes part of
Data captured by FPGA on rising SelectMap parallel
edge of CCLK.
peripheral interface.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
User I/O
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. If HSWAP = 1 in a
multi-FPGA daisy-chain
application, connect this signal to
a 4.7 kΩ pull-up resistor to
VCCO_2. Actively drives Low
when selecting a downstream
device in the chain.
BUSY
Output
Busy Indicator. Typically only
used after configuration, if
bitstream option Persist=Yes.
Not used during configuration but User I/O. If bitstream
actively drives.
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
88
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DS312-2 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
