R
Functional Description
After Configuration
Table 55: Serial Peripheral Interface (SPI) Connections (Continued)
FPGA
Pin Name
Direction
Description
During Configuration
Open-drain FPGA Configuration Done. Low during Low indicates that the FPGA is
DONE
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
bidirectional configuration. Goes High when FPGA
not yet configured.
I/O
successfully completes configuration.
Requires external 330 Ωpull-up resistor
to 2.5V.
Input
Program FPGA. Active Low. When
Must be High to allow
PROG_B
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
asserted Low for 500 ns or longer, forces configuration to start.
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns
programming access to SPI
Flash PROM pins.
High. Recommend external 4.7 kΩ
pull-up resistor to 2.5V. Internal pull-up
value may be weaker (see Table 78). If
driving externally with a 3.3V output, use
an open-drain or open-collector driver or
use a current limiting series resistor.
power supplies — V
, V
, and V
to I/O Bank 2
CCO
Voltage Compatibility
CCINT CCAUX
(VCCO_2) — to reach their respective power-on thresholds
Available SPI Flash PROMs use a single 3.3V supply volt-
age. All of the FPGA’s SPI Flash interface signals are within
I/O Bank 2. Consequently, the FPGA’s VCCO_2 supply volt-
age must also be 3.3V to match the SPI Flash PROM.
before beginning the configuration process.
The SPI Flash PROM is powered by the same voltage sup-
ply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
Power-On Precautions if 3.3V Supply is Last in
Sequence
accessed until their V
supply reaches its minimum data
CC
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 µs as shown in
Table 56. For other vendors, this delay is as much as 20 ms.
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in Figure 66. The FPGA waits for its three
Table 56: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
Data Sheet Minimum Time from V min to Select = Low
SPI Flash PROM
Part Number
CC
Vendor
Symbol
Value
10
Units
μs
STMicroelectronics
Spansion
M25Pxx
S25FLxxxA
NX25xx
T
VSL
t
10
ms
μs
PU
NexFlash
T
10
VSL
VSL
Macronix
MX25Lxxxx
SST25LFxx
t
10
μs
Silicon Storage Technology
T
10
μs
PU-READ
Programmable
Microelectronics Corporation
Pm25LVxxx
T
50
μs
VCS
Atmel Corporation
AT45DBxxxD
AT45DBxxxB
t
30
20
μs
VCSL
ms
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other V and
ever, if the 3.3V supply feeding the FPGA's VCCO_2 supply
is last in the sequence, a potential race occurs between the
FPGA and the SPI Flash PROM, as shown in Figure 55.
CCINT
V
supplies, and consequently, there is no issue. How-
CCAUX
DS312-2 (v3.8) August 26, 2009
www.xilinx.com
81
Product Specification
XILINX [ XILINX, INC ]
