R
Functional Description
Table 55: Serial Peripheral Interface (SPI) Connections
FPGA
Pin Name
Direction
Description
During Configuration
After Configuration
User I/O
Input
User I/O Pull-Up Control. When Low
during configuration, enables pull-up
resistors in all I/O pins to respective I/O
bank VCCO input.
Drive at valid logic level
throughout configuration.
HSWAP
P
0: Pull-ups during configuration
1: No pull-ups
Input
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
M2 = 0, M1 = 0, M0 = 1.
Sampled when INIT_B goes
High.
M[2:0]
User I/O
User I/O
Variant Select. Instructs the FPGA how Must be at the logic levels
VS[2:0]
to communicate with the attached SPI
Flash PROM. See Design
shown in Table 53. Sampled
when INIT_B goes High.
S
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
Output
Serial Data Output.
FPGA sends SPI Flash memory
read commands and starting
address to the PROM’s serial
data input.
MOSI
User I/O
User I/O
Input
Serial Data Input.
FPGA receives serial data from
PROM’s serial data output.
DIN
Output
Chip Select Output. Active Low.
Connects to the SPI Flash
PROM’s chip-select input. If
HSWAP = 1, connect this signal
to a 4.7 kΩ pull-up resistor to
3.3V.
CSO_B
Drive CSO_B High after
configuration to disable the
SPI Flash and reclaim the
MOSI, DIN, and CCLK pins.
Optionally, re-use this pin
and MOSI, DIN, and CCLK
to continue communicating
with SPI Flash.
Output
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity. See CCLK Design
Drives PROM’s clock input.
CCLK
User I/O
Considerations.
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of the
next FPGA in the chain.
DOUT
INIT_B
User I/O
Open-drain Initialization Indicator. Active Low.
bidirectional Goes Low at start of configuration during SPI Flash PROM requires > 2
Active during configuration. If
User I/O. If unused in the
application, drive INIT_B
High.
I/O
Initialization memory clearing process.
Released at end of memory clearing,
when mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
ms to awake after powering on,
hold INIT_B Low until PROM is
ready. If CRC error detected
during configuration, FPGA
drives INIT_B Low.
80
www.xilinx.com
DS312-2 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
