R
Functional Description
16x1 memory (RAM16) or as a 16-bit shift register (SRL16),
and additional multiplexers and carry logic simplify wide
logic and arithmetic functions. Most general-purpose logic
in a design is automatically mapped to the slice resources in
the CLBs. Each CLB is identical, and the Spartan-3E family
CLB structure is identical to that for the Spartan-3 family.
Configurable Logic Block (CLB) and
Slice Resources
For additional information, refer to the “Using Configurable
Logic Blocks (CLBs)” chapter in UG331.
CLB Overview
CLB Array
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB contains four slices, and
each slice contains two Look-Up Tables (LUTs) to imple-
ment logic and two dedicated storage elements that can be
used as flip-flops or latches. The LUTs can be used as a
The CLBs are arranged in a regular array of rows and col-
umns as shown in Figure 14.
Each density varies by the number of rows and columns of
CLBs (see Table 9).
X0Y3 X1Y3
X0Y2 X1Y2
X2Y3 X3Y3
X2Y2 X3Y2
X0Y1 X1Y1
X0Y0 X1Y0
X2Y1 X3Y1
X2Y0 X3Y0
Spartan-3E
FPGA
IOBs
Slice
CLB
DS312-2_31_021205
Figure 14: CLB Locations
Table 9: Spartan-3E CLB Resources
CLB
Rows
CLB
Columns
CLB
Total
LUTs /
Flip-Flops
Equivalent
Logic Cells
RAM16 /
SRL16
Distributed
RAM Bits
(1)
Device
Slices
960
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
22
34
46
60
76
16
26
34
46
58
240
1,920
2,160
5,508
960
2,448
4,656
8,672
14,752
15,360
39,168
74,496
138,752
236,032
612
2,448
4,656
8,672
14,752
4,896
1,164
2,168
3,688
9,312
10,476
19,512
33,192
17,344
29,504
Notes:
1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are
embedded in the array (see Figure 1 in Module 1).
LUTs support both logic and memory (including both
Slices
RAM16 and SRL16 shift registers) while half support logic
Each CLB comprises four interconnected slices, as shown
only, and the two types alternate throughout the array col-
in Figure 16. These slices are grouped in pairs. Each pair is
umns. The SLICEL reduces the size of the CLB and lowers
organized as a column with an independent carry chain.
the cost of the device, and can also provide a performance
The left pair supports both logic and memory functions and
advantage over the SLICEM.
its slices are called SLICEM. The right pair supports logic
only and its slices are called SLICEL. Therefore half the
DS312-2 (v3.8) August 26, 2009
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Product Specification
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