R
DC and Switching Characteristics
Table 105: Switching Characteristics for the DLL (Continued)
Speed Grade
-5
-4
Symbol
Description
Device
Min
Max
Min
Max
Units
Phase Alignment(4)
CLKIN_CLKFB_PHASE
CLKOUT_PHASE_DLL
Phase offset between the CLKIN and CLKFB inputs
All
-
-
200
-
-
200
ps
ps
Phase offset between DLL outputs CLK0 to CLK2X
(not CLK2X180)
[1% of
CLKIN
period
+ 100]
[1% of
CLKIN
period
+ 100]
All others
-
[1% of
CLKIN
period
+ 200]
-
[1% of
CLKIN
period
+ 200]
ps
Lock Time
LOCK_DLL(3)
When using the DLL alone: The
time from deassertion at the DCM’s
Reset input to the rising transition at
its LOCKED output. When the DCM
is locked, the CLKIN and CLKFB
signals are in phase
5 MHz < FCLKIN
15 MHz
<
All
All
-
-
5
-
-
5
ms
FCLKIN > 15 MHz
600
600
μs
Delay Lines
DCM_DELAY_STEP
Finest delay resolution
20
40
20
40
ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77 and Table 104.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum
jitter of " [1% of CLKIN period + 150]". Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of
10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250ps.
DS312-3 (v3.8) August 26, 2009
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145
Product Specification
XILINX [ XILINX, INC ]
