R
DC and Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 102: 18 x 18 Embedded Multiplier Timing
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Combinatorial Delay
T
Combinatorial multiplier propagation delay from the A and B
inputs to the P outputs, assuming 18-bit inputs and a 36-bit
product (AREG, BREG, and PREG registers unused)
MULT
(1)
(1)
-
4.34
-
4.88
ns
Clock-to-Output Times
T
Clock-to-output delay from the active transition of the CLK
input to valid data appearing on the P outputs when using
the PREG register
MSCKP_P
-
-
0.98
4.42
-
-
1.10
4.97
ns
ns
(2)
T
T
Clock-to-output delay from the active transition of the CLK
input to valid data appearing on the P outputs when using
either the AREG or BREG register
MSCKP_A
MSCKP_B
(3)
Setup Times
T
Data setup time at the A or B input before the active
transition at the CLK when using only the PREG output
register (AREG, BREG registers unused)
MSDCK_P
3.54
-
3.98
-
ns
(2)
T
T
Data setup time at the A input before the active transition at
the CLK when using the AREG input register
MSDCK_A
MSDCK_B
0.20
0.35
-
-
0.23
0.39
-
-
ns
ns
(3)
Data setup time at the B input before the active transition at
(3)
the CLK when using the BREG input register
Hold Times
T
Data hold time at the A or B input after the active transition
at the CLK when using only the PREG output register
(AREG, BREG registers unused)
MSCKD_P
–0.97
-
–0.97
-
ns
(2)
T
T
Data hold time at the A input after the active transition at the
CLK when using the AREG input register
MSCKD_A
MSCKD_B
0.03
0.04
-
-
0.04
0.05
-
-
ns
ns
(3)
Data hold time at the B input after the active transition at the
(3)
CLK when using the BREG input register
Clock Frequency
F
Internal operating frequency for a two-stage 18x18
MULT
multiplier using the AREG and BREG input registers and
the PREG output register
0
270
0
240
MHz
(1)
Notes:
1. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
DS312-3 (v3.8) August 26, 2009
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