R
DC and Switching Characteristics
Table 105: Switching Characteristics for the DLL
Speed Grade
-5
-4
Symbol
Description
Device
Min
Max
Min
Max
Units
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and
CLK180 outputs
Stepping 0
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
N/A
5
90
MHz
XC3S1200E
All
200
240
90
MHz
MHz
MHz
Stepping 1
Stepping 0
5
275
N/A
CLKOUT_FREQ_CLK90
CLKOUT_FREQ_2X
CLKOUT_FREQ_DV
Frequency for the CLK90 and
CLK270 outputs
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
5
XC3S1200E
All
167
200
180
MHz
MHz
MHz
Stepping 1
Stepping 0
5
200
N/A
Frequency for the CLK2X and
CLK2X180 outputs
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
10
XC3S1200E
All
311
311
60
MHz
MHz
MHz
Stepping 1
Stepping 0
10
333
N/A
Frequency for the CLKDV output
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
0.3125
XC3S1200E
All
133
160
MHz
MHz
Stepping 1
0.3125
183
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
Period jitter at the CLK0 output
Period jitter at the CLK90 output
Period jitter at the CLK180 output
Period jitter at the CLK270 output
All
-
-
-
-
-
100
150
150
150
-
-
-
-
-
100
150
150
150
ps
ps
ps
ps
ps
Period jitter at the CLK2X and CLK2X180 outputs
[1% of
CLKIN
period
+ 150]
[1% of
CLKIN
period
+ 150]
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing
integer division
-
-
150
-
-
150
ps
ps
Period jitter at the CLKDV output when performing
non-integer division
[1% of
CLKIN
period
+ 200]
[1% of
CLKIN
period
+ 200]
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock tree duty-cycle
distortion
All
-
[1% of
CLKIN
period
+ 400]
-
[1% of
CLKIN
period
+ 400]
ps
144
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DS312-3 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
