R
DC and Switching Characteristics
Digital Frequency Synthesizer (DFS)
Table 106: Recommended Operating Conditions for the DFS
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
0.200
333(4)
0.200
333(4)
MHz
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
F
F
CLKFX < 150 MHz
CLKFX > 150 MHz
-
-
300
150
-
-
300
150
ps
ps
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
-
1
-
1
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 104.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
Table 107: Switching Characteristics for the DFS
Speed Grade
-5
-4
Symbol
Description
Device
Min
Max
Min
Max
Units
Output Frequency Ranges
CLKOUT_FREQ_FX_LF
Frequency for the CLKFX and
CLKFX180 outputs, low frequencies
Stepping 0
XC3S100E
XC3S250E
XC3S500E
XC3S1600E
N/A
N/A
5
220
5
90
MHz
MHz
CLKOUT_FREQ_FX_HF
CLKOUT_FREQ_FX
Frequency for the CLKFX and
CLKFX180 outputs, high frequencies
307
Frequency for the CLKFX and
CLKFX180 outputs
Stepping 0
Stepping 1
XC3S1200E
All
307
311
MHz
MHz
5
333
Output Clock Jitter(2,3)
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and CLKFX180
outputs.
All
Typ
Max
Typ
Max
ps
ps
CLKIN
Note 6
≤20 MHz
[1% of
[1% of
[1% of
[1% of
CLKIN
> 20 MHz
CLKFX CLKFX CLKFX CLKFX
period
+ 100]
period
+ 200]
period
+ 100]
period
+ 200]
Duty Cycle(4,5)
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180
outputs, including the BUFGMUX and clock tree
duty-cycle distortion
All
-
[1% of
CLKFX
period
+ 400]
-
[1%of
CLKFX
period
+ 400]
ps
Phase Alignment(5)
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the
DLL CLK0 output when both the DFS and DLL are used
All
All
-
-
200
-
-
200
ps
ps
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the
DLL CLK0 output when both the DFS and DLL are used
[1% of
CLKFX
period
+ 300]
[1%of
CLKFX
period
+ 300]
146
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DS312-3 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
