R
DC and Switching Characteristics
Table 107: Switching Characteristics for the DFS (Continued)
Speed Grade
-5
-4
Symbol
Lock Time
Description
Device
Min
Max
Min
Max
Units
LOCK_FX(2)
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts
LOCKED when the CLKFX and
CLKFX180 signals are valid. If using
both the DLL and the DFS, use the
longer locking time.
5 MHz <
FCLKIN
15 MHz
All
-
5
-
5
ms
<
FCLKIN
>
-
450
-
450
μs
15 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77 and Table 106.
2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
3. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB
switching). Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB
utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on
the system application.
4. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
5. Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies
a maximum jitter of " [1% of CLKFX period + 300]". Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 300 ps] = 400 ps.
6. Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter.
Use the Clocking Wizard to determine jitter for a specific design.
Phase Shifter (PS)
Table 108: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Operating Frequency Ranges
PSCLK_FREQ
(F
Frequency for the PSCLK input
1
167
1
167
MHz
)
PSCLK
Input Pulse Requirements
PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period
40%
60%
40%
60%
-
Table 109: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Phase Shifting Range
MAX_STEPS(2)
Description
Equation
Units
Maximum allowed number of DCM_DELAY_STEP
steps for a given CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double the effective
clock period.
CLKIN < 60 MHz
CLKIN > 60 MHz
[INTEGER(10 • steps
(TCLKIN – 3 ns))]
[INTEGER(15 • steps
(TCLKIN – 3 ns))]
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
[MAX_STEPS •
DCM_DELAY_STEP_MIN]
ns
ns
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
[MAX_STEPS •
DCM_DELAY_STEP_MAX]
DS312-3 (v3.8) August 26, 2009
www.xilinx.com
147
Product Specification
XILINX [ XILINX, INC ]
