R
DC and Switching Characteristics
Table 99: CLB Distributed RAM Switching Characteristics
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Clock-to-Output Times
T
Time from the active edge at the CLK input to data
appearing on the distributed RAM output
SHCKO
-
2.05
-
2.35
ns
Setup Times
T
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
DS
0.40
0.46
0.34
-
-
-
0.46
0.52
0.40
-
-
-
ns
ns
ns
T
Setup time of the F/G address inputs before the active
transition at the CLK input of the distributed RAM
AS
T
Setup time of the write enable input before the active
transition at the CLK input of the distributed RAM
WS
Hold Times
T
Hold time of the BX, BY data inputs after the active
transition at the CLK input of the distributed RAM
DH
0.13
0
-
-
0.15
0
-
-
ns
ns
T
T
Hold time of the F/G address inputs or the write enable
input after the active transition at the CLK input of the
distributed RAM
AH, WH
Clock Pulse Width
, T Minimum High or Low pulse width at CLK input
T
0.88
-
1.01
-
ns
WPH WPL
Table 100: CLB Shift Register Switching Characteristics
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Clock-to-Output Times
T
Time from the active edge at the CLK input to data
appearing on the shift register output
REG
-
3.62
-
4.16
ns
Setup Times
T
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
SRLDS
0.41
-
0.46
-
ns
Hold Times
T
Hold time of the BX or BY data input after the active
transition at the CLK input of the shift register
SRLDH
0.14
0.88
-
-
0.16
1.01
-
-
ns
ns
Clock Pulse Width
, T Minimum High or Low pulse width at CLK input
T
WPH WPL
DS312-3 (v3.8) August 26, 2009
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Product Specification
XILINX [ XILINX, INC ]
