R
DC and Switching Characteristics
Table 97: Recommended Number of Simultaneously
Table 97: Recommended Number of Simultaneously
Switching Outputs per V
-GND Pair (Continued)
Switching Outputs per V
-GND Pair
CCO
CCO
Package Type
Package Type
FT256,
FT256,
FG320,
FG400,
FG484
FG320,
FG400,
FG484
Signal Standard
(IOSTANDARD)
VQ
100
TQ
144
PQ
208
CP
132
Signal Standard
(IOSTANDARD)
VQ
100
TQ
144
PQ
208
CP
132
LVCMOS18
Slow
2
4
6
8
2
4
6
8
2
4
6
2
4
6
2
2
19
13
6
11
7
8
6
29
19
9
64
34
22
18
36
21
13
10
55
31
18
25
16
13
55
31
16
13
11
17
16
15
18
Single-Ended Standards
LVTTL
Slow
Fast
Slow
Fast
2
4
34
17
17
8
20
10
10
6
19
10
7
52
26
26
13
13
6
60
41
29
22
13
11
34
20
15
12
10
9
5
5
6
4
4
9
6
Fast
13
8
8
8
19
13
6
8
6
5
5
12
16
2
8
6
5
4
4
4
5
5
5
4
4
4
6
17
9
17
9
17
9
26
13
13
6
LVCMOS15
LVCMOS12
Slow
Fast
16
8
10
7
10
7
19
9
4
6
7
7
7
6
5
5
9
8
6
6
6
9
9
9
13
7
12
16
2
5
5
5
6
7
7
7
5
5
5
5
5
5
5
5
LVCMOS33
34
17
17
8
20
10
10
6
20
10
7
52
26
26
13
13
6
76
46
27
20
13
10
44
26
16
12
10
8
Slow
Fast
17
10
8
11
10
8
11
10
8
16
10
16
13
11
16
16
15
18
4
6
PCI33_3
PCI66_3
PCIX
8
6
8
8
8
12
16
2
8
6
5
7
7
7
5
5
5
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
10
10
9
10
10
9
10
10
9
17
8
17
8
17
8
26
13
13
6
4
6
8
6
6
12
12
12
8
6
6
6
Differential Standards (Number of I/O Pairs or Channels)
12
16
2
5
5
5
6
8
8
5
5
LVDS_25
6
4
6
6
4
6
6
12
4
20
4
LVCMOS25
Slow
Fast
28
13
13
6
16
10
7
16
10
7
42
19
19
9
76
46
33
24
18
42
20
15
13
11
BLVDS_25
4
4
MINI_LVDS_25
LVPECL_25
6
12
20
6
Input Only
8
6
6
RSDS_25
6
5
5
4
6
6
5
5
4
6
6
5
5
4
6
12
8
20
8
12
2
6
6
6
9
DIFF_HSTL_I_18
DIFF_HSTL_IIII_18
DIFF_SSTL18_I
DIFF_SSTL2_I
17
9
16
9
16
9
26
13
13
6
8
8
4
7
7
6
9
7
7
9
8
8
6
6
6
Notes:
1. The numbers in this table are recommendations that assume sound
board layout practice. This table assumes the following parasitic
factors: combined PCB trace and land inductance per VCCO and GND
pin of 1.0 nH, receiver capacitive load of 15 pF. Test limits are the
VIL/VIH voltage limits for the respective I/O standard.
2. The PQ208 results are based on physical measurements of a PQ208
package soldered to a typical printed circuit board. All other results
are based on worst-case simulation and an interpolation of the
PQ208 physical results.
12
5
5
5
6
3. If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large FPGAs
for information on how to perform weighted average SSO
calculations.
DS312-3 (v3.8) August 26, 2009
www.xilinx.com
137
Product Specification
XILINX [ XILINX, INC ]
