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Spartan-3E FPGA Family:
Data Sheet
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DS312 (v3.8) August 26, 2009
Product Specification
Module 1:
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Introduction
Features
Architectural Overview
Package Marking
Ordering Information
Module 3:
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DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
Switching Characteristics
- I/O Timing
- SLICE Timing
- DCM Timing
- Block RAM Timing
- Multiplier Timing
- Configuration and JTAG Timing
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Module 2:
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Input/Output Blocks (IOBs)
- Overview
- SelectIO™ Signal Standards
Configurable Logic Block (CLB)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
Powering Spartan®-3E FPGAs
Production Stepping
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Module 4:
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Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
© 2005–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS312 (v3.8) August 26, 2009
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XILINX [ XILINX, INC ]
