Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 67: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
Speed Grade
-3 -2
Symbol
Description
Device
Units
-4
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode
and PLL in DCM2PLL Mode.
TICKOFDCM0_PLL
Global Clock and OUTFF with DCM and
PLL
XC6SLX4
N/A
N/A
N/A
N/A
5.57
N/A
5.53
N/A
5.55
N/A
5.62
N/A
5.32
5.95
5.94
6.06
6.04
6.04
5.97
5.97
6.00
6.00
6.03
6.03
5.70
5.70
7.00
7.00
7.05
7.02
7.02
6.96
6.96
6.99
6.99
7.02
7.02
6.41
6.41
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
N/A
N/A
N/A
N/A
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
DS162 (v1.9) August 23, 2010
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