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DS162 参数 Datasheet PDF下载

DS162图片预览
型号: DS162
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 6 FPGA数据手册:直流和开关特性 [Spartan-6 FPGA Data Sheet: DC and Switching Characteristics]
分类和应用: 开关
文件页数/大小: 73 页 / 2555 K
品牌: XILINX [ XILINX, INC ]
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics  
Table 65: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode  
Speed Grade  
-3 -2  
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode.  
Symbol  
Description  
Device  
Units  
-4  
-1L  
TICKOFPLL_0  
Global Clock and OUTFF with PLL  
XC6SLX4  
N/A  
N/A  
N/A  
N/A  
5.00  
N/A  
5.59  
N/A  
4.96  
N/A  
5.01  
N/A  
4.59  
5.81  
5.80  
5.77  
5.35  
5.35  
6.03  
6.03  
5.41  
5.41  
5.42  
5.42  
5.06  
5.06  
6.87  
6.86  
6.79  
6.10  
6.10  
7.02  
7.02  
6.22  
6.22  
6.21  
6.21  
5.86  
5.86  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
XC6SLX9  
XC6SLX16  
XC6SLX25  
XC6SLX25T  
XC6SLX45  
XC6SLX45T  
XC6SLX75  
XC6SLX75T  
XC6SLX100  
XC6SLX100T  
XC6SLX150  
XC6SLX150T  
N/A  
N/A  
N/A  
N/A  
N/A  
Notes:  
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible  
IOB and CLB flip-flops are clocked by the global clock net.  
2. PLL output jitter is included in the timing calculation.  
Table 66: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode  
Speed Grade  
Symbol  
Description  
Device  
Units  
-4  
-3  
-2  
-1L  
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode  
and PLL in DCM2PLL Mode.  
TICKOFDCM_PLL  
Global Clock and OUTFF with DCM and  
PLL  
XC6SLX4  
N/A  
N/A  
N/A  
N/A  
4.70  
N/A  
4.63  
N/A  
4.68  
N/A  
4.76  
N/A  
4.44  
5.01  
5.01  
5.12  
5.09  
5.09  
4.98  
4.98  
5.04  
5.04  
5.07  
5.07  
4.73  
4.73  
5.90  
5.89  
5.94  
5.92  
5.92  
5.83  
5.83  
5.88  
5.88  
5.92  
5.92  
5.31  
5.31  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
XC6SLX9  
XC6SLX16  
XC6SLX25  
XC6SLX25T  
XC6SLX45  
XC6SLX45T  
XC6SLX75  
XC6SLX75T  
XC6SLX100  
XC6SLX100T  
XC6SLX150  
XC6SLX150T  
N/A  
N/A  
N/A  
N/A  
N/A  
Notes:  
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible  
IOB and CLB flip-flops are clocked by the global clock net.  
2. DCM and PLL output jitter are already included in the timing calculation.  
DS162 (v1.9) August 23, 2010  
www.xilinx.com  
Advance Product Specification  
59  
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