Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 71: Global Clock Setup and Hold With PLL in System-Synchronous Mode
Speed Grade
Symbol
Description
Device
Units
-4
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
-3
-2
-1L
TPSPLL/ TPHPLL
No Delay Global Clock and IFF(2) with PLL XC6SLX4
in System-Synchronous Mode
N/A
N/A
N/A
N/A
2.07/
0.19
2.07/
0.19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6SLX9
2.06/
0.20
2.06/
0.20
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
1.53/
0.07
1.60/
0.07
1.71/
0.28
1.91/
0.28
1.70/
0.28
1.71/
0.28
1.91/
0.28
N/A
N/A
N/A
N/A
N/A
N/A
1.64/
0.18
1.75/
0.18
1.57/
0.18
1.64/
0.18
1.75/
0.18
N/A
1.89/
0.21
2.13/
0.21
1.80/
0.21
1.89/
0.21
2.13/
0.21
N/A
1.52/
0.32
1.70/
0.32
1.51/
0.32
1.52/
0.32
1.70/
0.32
N/A
1.48/
0.49
1.67/
0.49
1.41/
0.49
1.48/
0.49
1.67/
0.49
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS162 (v1.9) August 23, 2010
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