Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 22: GTP Transceiver Transmitter Switching Characteristics
Symbol
TRTX
Description
Condition
20%–80%
80%–20%
Min
–
Typ
140
120
–
Max
–
Units
ps
ps
ps
mV
ns
UI
TX Rise time
TX Fall time
TFTX
–
–
TLLSKEW
VTXOOBVDPP
TTXOOBTRANSITION
TJ3.125
TX lane-to-lane skew(1)
Electrical idle amplitude
Electrical idle transition time
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)
–
400
20
–
–
–
–
50
3.125 Gb/s
2.5 Gb/s
–
–
0.35
0.15
0.33
0.15
0.20
0.10
0.20
0.10
0.10
0.05
DJ3.125
TJ2.5
–
–
UI
–
–
UI
DJ2.5
–
–
UI
TJ1.62
1.62 Gb/s
1.25 Gb/s
614 Mb/s
–
–
UI
DJ1.62
–
–
UI
TJ1.25
–
–
UI
DJ1.25
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
–
–
UI
TJ614
–
–
UI
DJ614
–
–
UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP transceiver sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
Table 23: GTP Transceiver Receiver Switching Characteristics
Symbol
TRXELECIDLE
RXOOBVDPP
RXSST
Description
Min
–
Typ
75
–
Max
–
Units
ns
Time for RXELECIDLE to respond to loss or restoration of data
OOB detect threshold peak-to-peak
60
150
0
mV
Receiver spread-spectrum tracking(1)
Modulated @ 33 KHz
Internal AC capacitor bypassed
CDR 2nd-order loop disabled
–5000
–
–
ppm
UI
RXRL
Run length (CID)
–
150
200
2000
2000
1000
–200
–
ppm
ppm
ppm
ppm
PLL_RXDIVSEL_OUT = 1 –2000
PLL_RXDIVSEL_OUT = 2 –2000
PLL_RXDIVSEL_OUT = 4 –1000
–
Data/REFCLK PPM offset
tolerance
CDR 2nd-order
loop enabled
RXPPMTOL
–
–
(2)
SJ Jitter Tolerance
JT_SJ3.125
JT_SJ2.5
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
3.125 Gb/s
2.5 Gb/s
0.4
0.4
0.5
0.5
0.5
–
–
–
–
–
–
–
–
–
–
UI
UI
UI
UI
UI
JT_SJ1.62
1.62 Gb/s
1.25 Gb/s
614 Mb/s
JT_SJ1.25
JT_SJ614
Sinusoidal Jitter(3)
(2)(5)
SJ Jitter Tolerance with Stressed Eye
JT_TJSE3.125
JT_SJSE3.125
JT_TJSE2.7
JT_SJSE2.7
Total Jitter with stressed eye(4)
3.125 Gb/s
3.125 Gb/s
2.7 Gb/s
0.65
0.1
–
–
–
–
–
–
–
–
UI
UI
UI
UI
Sinusoidal Jitter with stressed eye
Total Jitter with stressed eye(4)
0.65
0.1
Sinusoidal Jitter with stressed eye
2.7 Gb/s
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. All jitter values are based on a Bit Error Ratio of 1e
–12
.
3. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
4. Composed of 0.37 UI DJ in the form of ISI and 0.18 UI RJ.
5. Measured using PRBS7 data pattern.
DS162 (v1.9) August 23, 2010
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