R
Platform Flash In-System Programmable Configuration PROMs
Revision
Date
Version
07/20/04
2.4
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Added Pb-free package options VOG20, FSG48, and VOG48.
Figure 6, page 16, and Figure 7, page 17: Corrected connection name for FPGA DOUT
(OPTIONAL Daisy-chained Slave FPGAs with different configurations) from DOUT to DIN.
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Section "Absolute Maximum Ratings," page 13: Removed parameter TSOL from table. (TSOL
information can be found in Package User Guide.)
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Table 2, page 3: Removed reference to XC2VP125 FPGA.
10/18/04
2.5
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Table 1, page 1: Broke out VCCO / VCCJ into two separate columns.
Table 9, page 9: Added clarification of ID code die revision bits.
Table 10, page 10: Deleted TCKMIN2 (bypass mode) and renamed TCKMIN1 to TCKMIN
Table "Recommended Operating Conditions," page 14: Separated VCCO and VCCJ parameters.
Table "DC Characteristics Over Operating Conditions," page 15:
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Added most parameter values for XCF08P, XCF16P, XCF32P devices.
Added Footnote (1) to ICCO specifying no-load conditions.
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Table "AC Characteristics Over Operating Conditions," page 16:
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Added most parameter values for XCF08P, XCF16P, XCF32P devices.
Expanded Footnote (1) to include XCF08P, XCF16P, XCF32P devices.
Added Footnote (8) through (11) relating to CLKOUT conditions for various parameters.
Added rows to TCYC specifying parameters for parallel mode.
Added rows specifying parameters with decompression for TCLKO, TCOH, TFF, TSF.
Added TDDC (setup time with decompression).
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Table "AC Characteristics Over Operating Conditions When Cascading," page 23:
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Added most parameter values for XCF08P, XCF16P, XCF32P devices.
Separated Footnote (5) into Footnotes (5) and (6) to specify different derivations of TCYC
depending on whether dual-purpose configuration pins persist as configuration pins, or
become general I/O pins after configuration.
,
03/14/05
2.6
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Added Virtex-4 LX/FX/SX configuration data to Table 2.
Corrected Virtex-II configuration data in Table 2.
Corrected Virtex-II Pro configuration data in Table 2.
Added Spartan®-3L configuration data to Table 2.
Added Spartan-3E configuration data to Table 2.
Paragraph added to FPGA Master SelectMAP (Parallel) Mode (1).
Changes to DC Characteristics
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T
I
V
OER changed, Page 15.
OL changed for VOL, Page 15.
CCO added to test conditions for IIL, IILP, IIHP,and IIH, Page 15. Values modified for IILP and
IIHP.
Changes to AC Characteristics
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T
LC and THC modified for 1.8V, Page 19.
New rows added for TCEC and TOEC, Page 18.
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Minor changes to grammar and punctuation.
Added explanation of "Preliminary" to DC and AC Electrical Characteristics.
07/11/05
12/29/05
2.7
2.8
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Move from "Preliminary" to "Product Specification"
Corrections to Virtex-4 configuration bitstream values
Minor changes to Figure 7, page 17, Figure 12, page 22, Figure 13, page 23, and Figure 16,
page 31
Change to "Internal Oscillator," page 8 description
Change to "CLKOUT," page 8 description
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Update to the first paragraph of "IEEE 1149.1 Boundary-Scan (JTAG)," page 5.
Added JTAG cautionary note to Page 5.
Corrected logic values for Erase/Program (ER/PROG) Status field, IR[4], listed under "XCFxxP
Instruction Register (16 bits wide)," page 5.
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Sections "XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock
Source," page 16, "XCFxxP PROM as Configuration Master with CLK Input Pin as Clock
Source," page 18 and "XCFxxP PROM as Configuration Master with Internal Oscillator as Clock
Source," page 21 added to "AC Characteristics Over Operating Conditions," page 16.
DS123 (v2.18) May 19, 2010
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Product Specification
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XILINX [ XILINX, INC ]
