R
Platform Flash In-System Programmable Configuration PROMs
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
04/29/03
06/03/03
11/05/03
11/18/03
Xilinx Initial Release.
Made edits to all pages.
Major revision.
1.1
2.0
2.1
Pinout corrections as follows:
•
Table 13:
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For VO48 package, removed 38 from VCCINT and added it to VCCO.
For FS48 package, removed pin D6 from VCCINT and added it to VCCO.
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Table 14 (FS48 package):
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For pin D6, changed name from VCCINT to VCCO.
For pin A4, changed name from GND to DNC.
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Figure 8 (VO48 package): For pin 38, changed name from VCCINT to VCCO.
12/15/03
05/07/04
2.2
2.3
Added specification (4.7kΩ) for recommended pull-up resistor on OE/RESET pin to section
"Reset and Power-On Reset Activation," page 11.
Added paragraph to section "Standby Mode," page 12, concerning use of a pull-up resistor
and/or buffer on the DONE pin.
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•
•
Section "Features," page 1: Added package styles and 33 MHz configuration speed limit to
itemized features.
Section "Description," page 1 and following: Added state conditions for CF and BUSY to the
descriptive text.
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Table 2, page 3: Updated Virtex®-II configuration bitstream sizes.
Section "Design Revisioning," page 8: Rewritten.
Section "Initiating FPGA Configuration," page 10 and following, five instances: Added instruction
to tie CF High if it is not tied to the FPGA’s PROG_B (PROGRAM) input.
•
Figure 6, page 16, through Figure 13, page 23: Added footnote indicating the directionality of the
CF pin in each configuration.
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Section "I/O Input Voltage Tolerance and Power Sequencing," page 11: Rewritten.
Table 12, page 25: Added CF column to truth table, and added an additional row to document
the Low state of CF.
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Section "Absolute Maximum Ratings," page 13: Revised VIN and VTS for ’P’ devices.
Section "Supply Voltage Requirements for Power-On Reset and Power-Down," page 13:
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Revised footnote callout number on TOER from Footnote (4) to Footnote (3).
Added Footnote (2) callout to TVCC
.
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Section "Recommended Operating Conditions," page 14:
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Added Typical (Typ) parameter columns and parameters for VCCINT and VCCO/VCCJ.
Added 1.5V operation parameter row to VIL and VIH, ’P’ devices.
Revised VIH Min, 2.5V operation, from 2.0V to 1.7V.
Added parameter row TIN and Max parameters
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(Continued on next page)
Section "DC Characteristics Over Operating Conditions," page 15:
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Added parameter row and parameters for parallel configuration mode, ’P’ devices, to ICCO
Added Footnote (1) and Footnote (2) with callouts in the Test Conditions column for ICCJ
ICCINTS, ICCOS, and ICCJS, to define active and standby mode requirements.
Section "AC Characteristics Over Operating Conditions," page 16:
.
,
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Corrected description for second TCAC parameter line to show parameters for 1.8V VCCO
Revised Footnote (7) to indicate VCCO = 3.3V.
Applied Footnote (7) to second TCYC parameter line.
.
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Section "AC Characteristics Over Operating Conditions When Cascading," page 23: Revised
Footnote (5)TCYC Min and TCAC Min formulas.
Table 14, page 39:
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Added additional state conditions to CLK description.
Added function of resetting the internal address counter to CF description.
DS123 (v2.18) May 19, 2010
www.xilinx.com
Product Specification
32