R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Virtex-II Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Setup and Hold for LVTTL Standard, With DCM
Table 36: Global Clock Setup and Hold for LVTTL Standard, With DCM
Speed Grade
Description
Symbol
Device
-6
-5
-4
Units
Input Setup and Hold Time Relative
to Global Clock Input Signal for
LVTTL Standard.
For data input with different
standards, adjust the setup time
delay by the values shown in IOB
Input Switching Characteristics
Standard Adjustments, page 11.
No Delay
TPSDCM/TPHDCM
XC2V40
XC2V80
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.96/–0.76
1.96/–0.76
1.96/–0.76
1.96/–0.76
1.96/–0.76
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Global Clock and IFF with DCM
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
DS031-3 (v3.5) November 5, 2007
Product Specification
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