R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
Table 35: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
Speed Grade
Description
Symbol
Device
-6
-5
-4
Units
LVTTL Global Clock Input to Output Delay using
Output flip-flop, 12 mA, Fast Slew Rate, without DCM.
For data output with different standards, adjust the
delays with the values shown in IOB Output Switching
Characteristics Standard Adjustments, page 14.
Global Clock and OFF without DCM
TICKOF
XC2V40
XC2V80
3.46
3.62
3.79
3.85
4.02
4.16
4.30
4.49
4.82
5.19
3.58
3.58
3.88
3.88
4.28
4.28
4.43
4.64
4.99
5.38
6.09
3.69
3.69
4.47
4.47
4.62
4.62
5.10
5.34
5.74
5.93
7.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with test setup shown in Figure 1. For other I/O standards, see Table 19.
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
32
XILINX [ XILINX, INC ]
