R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 14: IOB Input Switching Characteristics (Continued)
Speed Grade
-5
Description
Symbol
Device
-6
-4
Units
Propagation Delays
0.83
0.91
1.05
Pad to output IQ via transparent
latch, no delay
TIOPLI
All
ns, Max
TIOPLID
XC2V40
XC2V80
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.32
3.32
3.60
3.55
3.55
3.55
3.55
3.55
3.55
3.55
3.65
3.65
3.95
3.95
0.67
4.09
4.09
4.09
4.09
4.09
4.09
4.09
4.20
4.20
4.55
4.55
0.77
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Pad to output IQ via transparent
latch, with delay
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
All
TIOCKIQ
Clock CLK to output IQ
Setup and Hold Times With Respect to Clock at IOB Input
Register
0.84/–0.36
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.24/–2.04
3.33/–2.10
3.33/–2.10
3.61/–2.29
0.92/–0.39
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.57/–2.24
3.67/–2.31
3.67/–2.31
3.97/–2.52
3.97/–2.52
0.21/ 0.04
0.30
1.06/–0.45
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.10/–2.58
4.22/–2.66
4.22/–2.66
4.56/–2.90
4.56/–2.90
0.24/ 0.04
0.34
Pad, no delay
TIOPICK/TIOICKP
All
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
TIOPICKD/TIOICKPD
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
All
Pad, with delay
TIOICECK/TIOCKICE
TIOSRCKI
ICE input
All
0.27
SR input (IFF, synchronous)
Set/Reset Delays
SR input to IQ (asynchronous)
GSR to output IQ
Notes:
TIOSRIQ
TGSRQ
All
All
1.11
5.44
1.22
5.98
1.40
6.88
ns, Max
ns, Max
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18.
DS031-3 (v3.5) November 5, 2007
Product Specification
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